Analog Adaptive Neuron-Fuzzy Control Implementa- tiontion

Start

Layer 1:

Membership function calculation

Layer 2:

T-Norms calculation

Layer 3:

Normalization

Optimization (LSE)

i<P?

Training data (P: Samples)

Training data (P: Samples)

Y N

' 2 0

i i

turn turn i P

I I

 

 

Gradien Descent Method for Optimizing Premise Parameters

End

Figure 3.6: ANFIS training flowchart.

illustrated in the flowchart of3.6. This figure shows the flowchart of ANFIS learning al- gorithm with LSE and GDM learning methods. First of all, these input training samples go through layer 1-3 of ANFIS algorithm, and then LSE optimize the error square of the output samples, in compare with the desired output values. The consequence parameters are calculated to optimize the output errors. The following process is gradient-descent method (GDM) to update premise parameters of membership functions. The process in 3.6could be used in iteration in order to get better results.

3.3 Analog Adaptive Neuron-Fuzzy Control Implementa-

Chapter 3. The Proposed Cell Equalization...

t

VDD

I3

I4

I5

I2 I1

k1

V I0

Vin S1 2 V

VS S3

V

S4

V

k2 3 V

Vk k4

V

Figure 3.7: Fuzzy membership function impact circuit.

Figure 3.8: Simulation result of impact circuit current of membership functions.

Vk3 = 1.65V, and Vk4 = 2.15V, respectively as demostrated in 3.8. VB1 and volt- age derivationD_e are the inputs for the proposed controller.

The parameter set of{a^p_i, d^p_i}is updated from learning process in micro-processor as presented in the previous section.

a^p_i = V_k^p−1

i +V_k^p

i

2 , 2d^p_i =V_k^p

i −V_k^p−1

i (3.17)

• Layer 2:

I

1

I

2

I

min

V

_DD

Figure 3.9: 2−input loser-take-all minimum circuit.

As described in 3.5, the layer 2 is designed by minimum circuit. A loser-take-all minimum (LTA-MIN) circuit is built up in this layer. This circuit choose minimum fuzzy current from layer 1 according the rules of . This circuit is highly accurate, while achieving high current range without complexity. The circuit design and result are shown in 3.9. The values of 2 membership functions are the inputs to theLTA-MINcircuit. The resulting Imin is illustrated in 3.10

• Layer 3,4,5 or defuzzification:

The final output after the neuron layer 5 is calculated as:

y= P

i

α_is_i

P

i

α_i (3.18)

The consequent parametersi depends on defuzzification strategy. In the proposed AANFcontroller, a current-mode D/A converter is used as digitally-programmable singletonsi.

The output current of this circuit is expressed as follows:

Chapter 3. The Proposed Cell Equalization...

Figure 3.10: Result ofLTA-MINoutput current.

I_outⁱ =β_is_i= [n×(W/L)]×I_i

2ⁿ (3.19a)

Iout=

m

X

i=1

I_outⁱ =

m

X

i=1

βisi (3.19b) I_out=

m

X

i=1

(Dⁱ_n−12ⁿ⁻¹+...+Dⁱ₁2¹+Dⁱ₀2⁰)β_i

!

(3.19c)

3.11 shows the proposed circuit for singleton generators using 5-bit resolution D/A converter.

Where, mis number of rules. As aforementioned, the maximum number of rules is 25;

which N P (number of membership functions per input) is 5. These values of singletons for the output current are determined after the ANFIS learning process. Meanwhile, this learning process forms the input parameters of theANFISdefuzzification circuitry.

The (W/L) of the lower NMOSdevice rows in3.11 are equal to 1.

The divider circuit to form the equaltion3.18is based on the change of the drain current of a MOS transistor in strong inversion and triode region. The relations of current drain and gate-source voltage in weak and strong inversion are expressed in the following

I_i _i

V_DD

V_t I⁰ V_t I₁ V_t I₂ V_t I₃ V_t I₄ V_t

I_out

V_c

D0 D₁ D₂ D₃ D₄

Figure 3.11: 5−bit resolution D/A defuzzification circuitry.

Figure 3.12: Result of singleton generator output current with input varies from 0−10µA, and n= 32(D= 11111).

equations, respectively:

ID =µC0x

W L

(VGS−VT H)VDS −V_DS² 2

(3.20a) ID = 1

2µC0x

W

L(VGS−VT H)² (3.20b)

Chapter 3. The Proposed Cell Equalization...

Ix

Iy Iw

x y

k I I

g-mean Squarer/ Iz

Divider

Figure 3.13: Current-mode multiplier/divider concept diagram.

The approach to implement the current-mode multiplier/divider is combination of a geometric-mean circuit and a squarer/divider circuit as describled in 3.13. It is able to calculate the geometric mean of two currents:

I_out = k√

I_XI_Y2

k²I_W (3.21)

and then the output current of g-mean circuit is introduced to a squarer/divider circuit.

Overall, the output of the divider is calculated as:

I_out =I_XI_Y/I_W (3.22)

The concept in 3.13 could be designed by forcing proper transition from triode region to saturation region of MOSFET [28]. Since the drain current is proportional to gate- source voltage in triode region, and proportional to square of gate-source voltage in saturation region. 3.15 shows the implementation of the divider concept in 3.13. Since the concept of divider circuit is based on transition working region of MOSFET, it is important to evaluate the working conditions and working regions of each transistors in circuit. The transistorsM1A,M1B,M1C,M1Dare forced to saturation region by chosing proper value of V_CN. At the half circuit in the left (including a-b MOSFET devices), the drain-source voltage of transistorM_2A, and M_2B are calculated as following:

V_DS2,a =V_GS1,b−V_GS4.b = s

2I_y β −

s 2I₂ n²β =

r2 β

pI_y−

√I₂ n

(3.23a) n²= (W/L)_M3−4

(W/L)_M1−2 (3.23b) V_DS2,b=V_GS1,a−V_GS4.a =

s 2Ix

β − s

2I1

n²β = r2

β

pIx−

√I1

n

(3.23c) For the largen, when I_X < I_Y,M_2A will operate in triode region whileM_2B is in satu- ration region. When IX < IY, M2A is in saturation region whileM2B in triode region.

Considering the case of (I_X < I_Y), when the M_2B in saturation, therefore, I₁ = I_Y. Hence, for the largen, the summation of current is:

Chapter 3. The Proposed Cell Equalization...

Bien’s Integrated Circuit Design Lab

^33/50

 Layer 3-4-5: Defuzzification

 Current-mode Divider: Simulation result

x y out

w

I I I

 I

1 2 2 _{x y}

I I  I I

DC Response

Iy (µA)

Current output(µA)

Iw=5(µA) Ix = 10(µA)

x y out

w

I I I

 I

Figure 3.14: Current-mode divider circuit simulation result.

I1+I2 ∼= 2p

IxIy (3.24)

The same geometric-mean cell but configured as a squarer/divider. With an analogous analysis, the following equation can be found:

I₁+I₂ ∼= 2p

I_wI_out (3.25)

Finally, the output current is calculated as dividing ofI_out = ^Ix_I^Iy

w . The figure3.14shows the result of the current-mode divider implementation withIW = 5µA,IX = 10µAwhile I_Y varies from (0∼20µA).

The total energy consumption by theANFISblock is expressed in the following equation:

P ≤n(3m−4)VDDI_o^max (3.26)

WhileVDD = 2.5V andIomax= 12µA. Therefore, the total loss power forAANFis less thean 4.26mW which is insignificant in compare with the total power of system.

The overall BMS system with parameter and signal flows is illustrated in3.16. Thanks to the parallel and modular characteristic, only two battery cells with ICE are demostrated.

In the proposed system, the voltage sensor block is composed of voltage sensors for battery cells, ANFISlearning algorithm is constructed with a micro-processor, and the AANFblock is designed in a 0.13−µm CMOS technology with power supply of 2.5V.

Chapter 3. The Proposed Cell Equalization...

Ix Iy Iw Iout

VDD

GND

VP

VC VC VC VC

M3a

M1a

M4a

M2a M2b

M4b

M3b M1b

M3c

M1c

M4c

M2c M2d

M4d M3d

M1d

I1 I2 I1' I2'

Figure 3.15: Current-mode divider circuit implementation.

Voltage sensor

PWM

Layer 3,4,5 Layer 1

ANFIS learning

1 0 1 0

si

Itune

VBD_e

VBD_e

Layer 2 MIN MIN MIN MIN MIN MIN

Vk

AANF

Micro-processor

ICE_1

B1

V

B2

V

Battery pack with ICE_1

Figure 3.16: Proposed system with parameter and signal flows.

System Performance Results