CHAPTER 5. CELL-BASED DESIGN FLOW (CBDF) WITH ANALOG
5.2. CBDF E XAMPLE : T IME - BASED P IPELINED ADC
The prototype time-based pipelined ADC in chapter 4 was made by CBDF with ACL. The core MDAC’s pin description and specification are described in Fig. 5.3. As can be seen in Fig. 5.3, MDAC has mostly digital-type inputs and outputs even if its internal functionality is highly dependent on analog.
Figure 5.3: MDAC’s pin description and specification.
128
Time-domain digital signal such as clock or pulse is insensitive to process, volt- age, and temperature (PVT) variation and voltage-domain noise so that it gives possibility to connect each other or any digital CMOS circuits by automatic P&R without considering any constraints (i.e., loading effect). The MDAC’s Figure 5.4: MDAC’s behavioral model.
Figure 5.5: N-bit time-based ADC example.
Figure 5.6: Layout of ADC core.
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behavioral model described in XMODEL is shown in Fig. 5.4.
Fig. 5.5 shows time-based ADC core using combination of ACL cells (VTC, cascaded MDACs). Since the internal operation of each cell is isolated due to pulse input / output environment, ADC can be implemented by simply cascad- ing the ACL cells. The resolution can be arbitrarily adjusted by changing the stage number (N) according to the demand of the user. In layout aspect, it is possible to implement the pipelined ADC core simply by connecting the ACL cells (Fig. 5.6) in P&R stage.
Those macro cells are placed semi-manually (but, easily) based on the sys- tem floorplan while the placement of the rest of the cells such as the standard logic cells can be left to the automation tool. Then, the critical signal traces such as the high-speed signal inputs, multi-phase clocks, and sensitive bias lines that require careful matching and isolation from interferences are manually pre- routed. The other less critical signals can be routed automatically. The power network routing and filler cell insertion are performed next. This sequence is far more advanced than what any analog layout tools can offer. Except for some cell placements and sensitive wire routing, most of the physical design process is automated, leveraging the system’s functional model (i.e., Verilog or System Verilog) as the structural netlist.
As seen before, Fig. 4.30 shows the final layout of the time-based ADC con- structed by using this flow and Fig. 4.32 shows the final simulation results (transient and ENOB) after auto P&R, respectively.
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Chapter 6.
Conclusion
This dissertation presented novel digital-driven design techniques for solv- ing various systematic defects in digital PLL and CDR circuitries
In Chapter 2, the design and analysis of the peaking-free DPLL has been presented. The necessary phase compensation feedback is implemented solely using a new type of digital loop filter without adding any noise-sensitive analog components on the clock paths. Furthermore, the mixed-signal circuit technique to keep TDC characteristic insensitive to PVT or input jitter is presented. The linear TDC is implemented as DSM-dithering based oversampling technique, which uses the combination of phase DAC and DSM to generate pseudo-ran- dom time-varying offset. By exploiting this, the linear and constant TDC gain is achieved in a statistical sense. The measurement results show that the pro- posed PLL can achieve fast settling without exhibiting a phase-domain over- shoot.
In Chapter 3, a novel digital auxiliary circuit for SSC tracking has been pre- sented. It achieves accurate and noise-resilient performance, whereby the SSC deflection points are restored by an IBMT loop. By analyzing and simulating IBMT’s frequency response, the proposed SSC tracking aid can be designed to exhibit a timing error as low as 0.01% of the SSC period and to withstand noisy
131
SSC profiles in which SNDR is as low as 20 dB. The simulation results shows that a PLL-based CDR with the proposed SSC tracking aid achieves remarkably suppressed timing error in comparison with a second-order counterpart.
In Chapter 4, a new-type time-domain MDAC, combination of I&F unit and CMOS logic gates, has been firstly presented. By exploiting time-domain pulse modulation, it can achieve highly constant and calibration-free 2× residue am- plification in low cost way. Time-based pipelined ADC with this unit cell is power-area efficient and simple to be calibrated because it also take advantage of time-domain operation. Lastly, SS-DPLL employing the pipelined ADC also reduces hardware complexity and power by replacing the flash ADCs and pe- ripheral circuits with the time-based ADC. The simulation results how that ADC and PLL’s FOMs are competitive enough compared with those of state- of-the-arts ADC and PLL.
In Chapter 5, mixed-signal version cell-based design flow and analog cell library are introduced. The well-organized design flow and cell library enable us to exploit automatic place-and-route using existing EDA tool as well as top- level system verification with XMODEL.
132
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초 록
본 학위 논문은 디지털 방식의 위상동기루프 (PLL) 와 데이터
및 클럭 복원 회로 (CDR)의 분야 전반에 걸친 여러 시스템상 취
약점들을 참신한 디지털 및 혼성신호 회로들을 도입해서 해결한 점에서 의의가 있다. 기존의 아날로그 설계의 접근 방식과는 다 르게 디지털 기술들의 확장성 또는 프로그래밍 가능성을 이용하 면 이러한 타이밍 회로들의 설계 제한 조건들을 완화시킬 수 있 다. 가령, 매우 간소화된 캘리브레이션 구현이나, 특수한 전달 함 수 및 비선형 특성의 구현 같은 것들이 대표적인 예제이다. 본 연구가 디지털 및 디지털 중심의 혼성신호 회로를 이용해서 해결
한 문제들은 PLL의 전달함수 특성 개선, 스프레드 스펙트럼 변조
된 (SSC) 데이터 수신 CDR 의 추적 (tracking) 능력 개선, 파이프 라인 아날로그-디지털 변환기의 2× 잔류 증폭의 특성 개선, 서브- 샘플링 위상 동기 루프의 전력 및 면적 개선 등에 걸쳐 있다.
첫째로, 본 논문은 peaking 이 없는 전달함수를 가진 디지털 PLL
의 설계를 제안하였다. 기존의 2차 PLL이 가지는 폐루프의 전달 함수의 영점을 제거함으로써, 위상 영역에서는 오버슈트를 제거 함으로써 빠른 안정화 속도를 달성하였고, 주파수 영역에서는 지 터 피킹을 제거하여 인밴드 노이즈의 증폭을 막는 솔루션을 제안 하였다. 기존에 발표되었던 연구들과는 다르게, 제안하는 디지털
PLL 의 peaking 이 없는 전달함수는 오직 디지털 필터만 개선하여
달성하였다. 또한, 이 디지털 PLL 에는 시그마-델타 모듈레이터와
140
위상-디지털 변환기를 이용하여, 시간에 따라 변하는 (time-varying)
오프셋을 가진 과샘플링 (oversampling) 클럭으로 위상 오차
(phase error)를 선형적으로 변환하는 시간-디지털 변환기 (TDC)가 제안되었다. 이 TDC 는 하드웨어 비용이나, 공정, 전압, 온도, 그
리고 지터에 상관없는 일정한 TDC 전달 함수 구현이 가능하다.
제안된 PLL 은 65nm 저전력 CMOS 공정으로 제작되었으며, 측정
결과는 1.58μs의 매우 빠른 안정화 속도를 나타낸다.
둘째로, 본 논문은 큰 스프레드 스펙트럼 변조가 (SSC) 인가된
데이터를 수신하는 수신기가 큰 타이밍 마진을 가지고 데이터를 추적하도록 하기 위하여, 별도의 디지털 컨트롤러의 설계를 제안
하였다. 제안하는 SSC 추적을 위한 디지털 컨트롤러는 적분-기반
평균-추적 알고리즘을 구현함으로써, 잡음에 대해 내성을 가지며
정확한 SSC 타이밍을 복원이 가능하게 된다. 이 구조의 분석에
따르면, 0.01%의 오차로 SSC의 타이밍을 복원 하며, 20-dB의 신호
-잡음-외란 비율 (SNDR)의 잡음이 가해질 때도 타이밍 오류가
1.5%를 벗어나지 않는다. 이를 적용한 전체 CDR 에 대한 시뮬레
이션 결과는 30kHz, 50,000-ppm 의 SSC 데이터가 인가될 때, 일반 적인 PLL 기반의 2차 CDR과 비교하였을 때 1.57배 개선된 타이 밍 마진을 가진다.
셋째로, 본 논문은 새로운 시간-베이스의 파이프라인 ADC 를 적
용한 서브-샘플링 디지털 PLL 의 설계에 대해서 소개한다. 주요
회로인 멀티플라잉 디지털-아날로그 변환기 (MDAC)는 시간-도메 인 설계를 가능하게 하는 인테그레이트 앤 파이어 (I&F) 회로와 디지털 로직 게이트들을 조합하여 매우 안정적이고 이득의 캘리