Ⅲ. Design of an On-die Oscilloscope Circuit for System-Level Transient ESD Noise
3.4 Validation of Chip Operations in Measurement
The designed circuit is implemented in 180 nm CMOS technology for testing in measurement. Fig.
45 shows the layout of the designed circuit and fabricated die chip and packaged IC as metric quad flat pack (MQFP) type. The sizes of die chip and package are 3.8mm × 3.8mm and 30.6 mm × 30.6 mm, respectively. There are 208 pins in package and only 66 pins are needed for the operation. Also, over 20 pins are used for controlling the operation of chip. The layout of a designed test PCB for validation of the chip operations is shown in Fig. 46 (a) where the size of a test PCB is 112 mm × 110 mm. Fig.
46 (b) shows the test PCB and a picture of a die chip bonded to the PCB. In case of package, the longer wire bonding makes the parasitic inductances between PCB pads and pins of chip which would cause the distortion at high frequency and inaccurate measurement results.
(a) (b)
Fig. 45. (a) Layout of the designed circuit in 180nm technology (b) Die chip and packaged IC with size
(a)
(b)
Fig. 46. (a) Layout of a test PCB for validation of the chip operations (b) Test PCB and a die chip bonded to the PCB
Fig. 47 shows the measurement setup for testing the operation of capturing the noise waveform in the designed circuit. Testing of the designed circuit is performed in three steps. First, the operation of DLL circuit block will be checked from the low frequency to high frequency. The clock signal for reference clock of DLL is applied to the chip from a pulse pattern generator (PPG). The expected highest locking frequency from the simulation was up to 800 MHz. But, due to several problems in circuit design process, the maximum possible clock frequency is about 300 MHz in measurement. Then, sinusoidal signals with various frequencies are applied into signal line of the chip from the signal generator. Because of low frequency of sampling clocks, the available frequency in sinusoidal signals is limited below 600 MHz. Fig. 48 shows the comparison between the applied signals from signal generator and the recovered waveforms from the on-die oscilloscope circuit at 50 MHz and 100 MHz sinusoidal signals. The offset levels of recovered waveforms are adjusted. As shown in Fig. 48 (b), the ability of waveform capturing is under the designed specification. In detail, -3dB frequency in waveform recover was about 63 MHz.
Fig. 47. Measurement setup for validation of operations of the designed circuit
(a) (b)
Fig. 48. The comparison between the applied sinusoidal signals and the recovered waveforms from the on-die oscilloscope circuit (a) at 50 MHz and (b) 100 MHz
Fig. 49 shows the test setup for ESD detector circuit at power supply line. As a noise source, TLP signals described in section II are utilized for finding the detection range. Fig. 50 shows the measured voltages at VDD and detect signals when the pulse width is set as 5.4 ns in TLP generator. Due to low impedance at VDD-GND, the large portion of the noise signal is reflected, and then, the reflected signal is injected again into ESD detector circuit at power supply line. By multiple reflections, the measured voltages at VDD show the ringing shape with several noise pulses. As shown in Fig. 50 (b), if the voltage level of the first noise pulse is over the threshold, the detect signal is switched from low to high level. Fig. 51 represents comparison of detection threshold curves between circuit simulation and measurement. The procedure of extraction of threshold curve is equal to that in section II. In simulation, the threshold curve is flat up to pulse width of 2 ns. The threshold level increased sharply in the shorter pulse width. The threshold curve in measurement also shows the almost flat shape up to pulse width of 5.4 ns. But, due to problems in circuit design process, the results below 5 ns cannot be obtained.
Fig. 49. Test setup for ESD detector circuit at power supply line
(a) (b)
Fig. 50. The measured voltages at VDD and detect signals when the pulse width is set as 5.4 ns in (a) No detect case and (b) Detect case
Fig. 51. Comparison of detection threshold curves between simulation and measurement
Fig. 52 shows the test setup for ESD detector circuit at signal line. As in case of ESD detector circuit at power supply line, TLP signals are utilized for finding the detection range. But, due to the soldered resistor on test PCB, the impedance at SIG-GND is almost 50 Ω and the reflection issue does not need to consider. Fig. 53 and Fig. 54 represent the measured voltages at SIG and detect signals from positive and negative sensors when the pulse width is set as 5 ns, respectively. The comparisons of threshold curves from simulation and measurement in positive and negative sensors are shown in Fig. 55. The procedure of extraction of threshold curves is same as previous ESD detector case. The minimum pulse width in measurement is about 0.6 ns because of limitation in TLP generator. In the common pulse width range, the shapes of threshold curves are nearly flat. There are just small discrepancies in simulation and measurement, which is caused by difference in test environment.
Fig. 52. Test setup for ESD detector circuit at signal line
(a) (b)
Fig. 53. The measured voltages at SIG and detect signals from positive sensor when the pulse width is set as 5 ns in (a) No detect case and (b) Detect case
(a) (b)
Fig. 54. The measured voltage at SIG and detect signal from negative sensor when the pulse width is set as 5 ns in (a) No detect case and (b) Detect case
(a) (b)
Fig. 55. Comparisons of threshold curves from simulation and measurement in (a) positive sensor and (b) negative sensor