SiC Schottky barrier diode is the first SiC device. [4, 44] SiC Schottky diode takes a crucial role in high-power, high-temperature devices because of its superior electrical, physical properties as described in previous chapter. [45-47] The breakdown voltage limit for conventional silicon Schottky diode is less than 200V but in case of SiC Schottky diode, is up to 10 times compare to silicon. Silicon carbide diodes were widely used for solar power conversion before active research on high voltage devices, including automobiles. High voltage diodes play a key role in solar energy converters, boost circuits, UPSs, charging systems, and automotive applications that are currently being studied most actively.
A crucial merit for SiC compare to other materials including GaN is compatibility for conventional processes of silicon. [48] SiC is preferred over GaN in the market, so SiC power semiconductors are partially commercialized and sold while GaN-based power semiconductor technology is not yet commercialized in its early stages. The physical properties of these materials are similar, but one of the reasons SiC is drawing attention is the type of bandgap. GaN is direct bandgap semiconductor which is more suitable features for use in devices through light than power semiconductor. SiC has the same direct bandgap property as silicon. SiC also has a very high thermal conductivity that is three times as high as thermal conductivity of Si or GaN. High voltage devices inevitably generate a lot of heat, so they must operate reliably at high temperatures, which is also very beneficial in terms of cooling efficiency. The breakdown voltage in commercialized Si Schottky barrier diode is limit around 200 V, while SiC is 1200~1700V.
32
TABLE 4. Electrical properties of silicon, 4H-SiC, and GaN which are mostly used in high-power devices.
Properties Silicon 4H-SiC GaN
Crystal structure Diamond Hexagonal Hexagonal
Band gap type Indirect Indirect Direct
Band gap energy (eV) 1.12 3.26 3.5
Electron mobility (cm2/V s) 1400 950 1250
Hole mobility (cm2/V s) 600 100 200
Thermal conductivity (W/cm ℃) 1.5 4.9 1.3
Relative dielectric constant 11.8 9.7 9.5
Breakdown Field (V/cm) 0.3×106 3.2×106 3.0×106
Saturation drift velocity (cm/s) 1×107 2.7×107 2.7×107
Thermal oxide O O X
33
4.2 Ni/4H-SiC Schottky Barrier modulation by Thin AlN Layer
There have been various tries to modulating Schottky barrier (
B) by inserting passivation layers. [6, 9, 49-52] The Schottky barrier height is very crucial because the electrical characteristic is strongly depend on the Schottky barrier height. [53] Though the Schottky barrier height is proportional to the metal work function, due to the Fermi-level Finning effect, there is a significant limitation in adjusting the Schottky barrier height. Considering Fermi-level pinning effect, the Schottky barrier can be expressed as( ) ( )
B S M CNL CNL S
(15)Where S is the pinning factor,
M is metal work function,
CNL is charge neutrality level of semiconductor, and
S is the electron affinity of semiconductor. [54] The pinning factor of n-type 4H-SiC is known to be between 0.6 and 0.7. [6] Additionally, the spontaneous polarization, as well as the metal work function or the pinning factor, also has a significant effect on the barrier. By inserting additional layer, it is possible to adjust the spontaneous polarization with various mechanisms.Lower Schottky barrier height is advantageous to avoid unnecessary power consumption. [55] The sample fabrication processes are described in Chapter 3. After the sputtering and post-annealing, 50 nm thickness of nickel is deposited by e-beam evaporator with 500 um dot patterned shadow mask. Figure 24 shows the current-voltage graph of substrate contact on the C-face. The resistance is measured below 10 Ω. We used n-type 4H SiC wafer with 0.5 µm of buffer layer with n-type 1×1018 cm-3 and 17.8 µm of epi-layer with n-type 2×1015 cm-3. The epi layers were grown on 8.06° miscut Si-face.
Figure 24 I-V graph of substrate Ohmic contact on C-face of 4H-SiC
34 4.2.1 I-V Measurement
Figure 25 and 26 show the I-V characteristic of Ni/SiC Schottky diode with ultra-thin interfacial aluminum nitride film respect to the sputtering time. Significant Schottky barrier reduction occurred.
The remarkable is the negligible change in on-current and leakage-current regardless the AlN film. The bare Ni/SiC sample has Schottky barrier with 1.721 eV and the barrier is decreases as the time of sputtering increased. After 120 sec, the barrier is rather increased and the ideality factor become higher, and the current density significantly decreased. There is a report that PbS thin layer between Au/6H- SiC Schottky diode decreases the Schottky barrier by 0.09 eV [52], and TiO2 thin film between Ni, Ti, Al/4H-SiC Schottky diode also decreases the barrier by 0.2~0.3eV but significantly increases the reverse leakage current. [6, 56]
After more than 150 sec of deposition the Schottky barrier even more increased and show very weird curve of plot. All samples except the sample of 150 sec sample show almost match to 1, which imply overall carrier transport process is obey on the thermionic emission. As the voltage is increased, Ni/SiC samples with interfacial layer show somewhat rounded shape of curve, which can be estimated as a tunneling and recombination. The barrier is significantly decreased reaching 0.66 eV while remaining high on current. As the thickness is increases, the current density tends to decreases but almost same until 90 sec. The reverse leakage current is below the limit for the SMU 2636A which has 10-13 of minimum current resolution and the current density was calculated with 500 um diameters of circle.
The current is measured with hysteresis with 530 ms of delay and 0.01 mV of step to reduce the noise.
Each sample has measured with at least 3 different dots and 3 times for same dots.
TABLE 5. Extracted Schottky barrier and ideality factor by I-V measurement with respect to the aluminum nitride deposition time.
Sample I-V Barrier (eV) Ideality factor Current density in 2.2V bias (A)
0 sec 1.710±0.013 1.035±0.010 37.98±15.17
30 sec 1.220±0.010 1.035±0.005 46.73±7.34
60 sec 1.113±0.014 1.034±0.004 41.04±4.03
90 sec 1.045±0.003 1.020±0.006 47.92±1.34
120 sec 1.048±0.014 1.022±0.009 27.44±1.68
150 sec 1.399±0.064 1.257±0.134 0.36±0.11
35
Figure 25 I-V graph for Ni/SiC Schottky barrier diode with ultra-thin AlN interlayer for (a) without AlN, (b) 30 sec, (c) 60 sec, (d) 90 sec, (e) 120 sec, (f) 150 sec of deposition (sputtering).
36
Figure 26 I-V graph for Ni/SiC Schottky barrier diode with ultra-thin AlN interlayer in (a) logarithm and (b) linear scale.
37 4.2.2 C-V Measurement
Figure 27 and 28 show the C-V characteristic of the sample with different time of sputtering. The capacitance of C = dQ/dV is measured by applying reverse bias and AC voltage with 50 mV of amplitude and 1 MHz of frequency with E4980a LCR meter. The reverse bias is sweep from 0 V to 3 V. The capacitance data is converted to 1/C2 in the graph to find the Schottky barrier. By using the equation (12),
2
( 2) 2
S D
bi
q N A
V V
C
, then the build-in potential is the x-intercept of the A/C2 graph.As a result, very similar parameter is extracted compare to the I-V measurement. The Schottky barrier significantly decreased reaches 0.72 eV. The targeted doping concentration is 2×1015 cm-3, and the measured results indicate reasonable doping concentrations, 2.73×1015 cm-3~3.3×1015 cm-3. The measured doping concentration tends to bigger as the deposition time increased. As in the case of I-V measurement, the Schottky barrier become higher after the 150 sec of deposition. 1/C2 versus bias voltage graph shows very linear shape but when the deposition time exceeds 150 seconds, the bending near the 0 V of bias is observed. C-V measurement is successively performed following I-V measurement. The capacitance measured 5 times with 3 different dots for 1 sample.
TABLE 6. Extracted Schottky barrier and Nd by C-V measurement with respect to the aluminum nitride deposition time.
Sample C-V Barrier (eV) Nd (×1015 cm-3)
Reference 1.746±0.006 2.835±0.017
30 sec 1.217±0.037 2.901±0.031
60 sec 1.089±0.014 2.775±0.030
90 sec 1.025±0.002 2.734±0.030
120 sec 1.026±0.021 3.279±0.029
150 sec 1.521±0.007 3.299±0.086
38
Figure 27 C-V graph for Ni/SiC Schottky barrier diode with ultra-thin AlN interlayer for (a) without AlN, (b) 30 sec, (c) 60 sec, (d) 90 sec, (e) 120 sec, (f) 150 sec of deposition (sputtering).
39
Figure 28 C-V graph for Ni/SiC Schottky barrier diode with ultra thin AlN interlayer
4.2.3 IPE Measurement
Internal photoemission measurements with range of 1.1 eV ~ 1.8 eV and 1.55 eV~ 2.07 eV have performed. Yield1/2-photon energy graph is shown in Figure 29. Typical silicon carbide Schottky diode shows two barriers. [19] The dash line indicates the linear interpolation procedure of yield1/2. Because
1/2
Y hv q
B, the x-intercept can be extracted as a barrier. The first region is believed as the Schottky barrier. [57] There can exist additional barriers originated in the crystal field splitting of the SiC. [58]The total photocurrent yield can be express Ytotal1/2
Yi1/2
A hv qi(
B) , where Yi1/2 is ith barrier with some arbitrary constants, Ai. There exist two or more linear part in the Yield1/2-photon energy graph, and the intersection of the first/second, second/third are the second, third barrier.40
Figure 29 Yield-photon energy graph for Ni/SiC Schottky barrier diode with ultra-thin AlN interlayer for (a) without AlN, (b) 30 sec, (c) 60 sec, (d) 90 sec, (e) 120 sec, (f) 150 sec of deposition (sputtering).
The red circle indicates the different range of measurement.
41
Figure 30 Schottky barrier of Ni/SiC with very thin AlN interlayer, according to the AlN deposition time by CV, IV, and IPE measurement.
4.2.4 Schottky barrier
To sum up the results, the Schottky barrier is clearly decreased by more than 0.6 eV suppressing the leakage current and remaining the on-current. The ideality factor indicates most of carrier transport mechanism is based on the thermionic emission. Current-voltage, capacitance-voltage, and IPE measurement indicate same result. This is remarkable because there have been researches to adjust the Schottky barrier, [6, 9, 52] but the significant reduction of on-current or increasement of leakage current happened. The low ideality factor indicates the carrier transport mechanism is dominated by thermionic emission but as the deposition time increased, the Schottky barrier and ideality factor simultaneously are increased.
The Schottky barrier of Ni/4H-SiC without any interfacial layer is measured as 1.710±0.013 for I-V, 1.746±0.006 for C-V, and 1.600±0.006 for IPE. For all the samples, the Schottky barriers of IPE are estimated larger than the Schottky barrier of I-V and C-V measurements. As the deposition time increased, all measurements show the lowest Schottky barrier at the deposition time of 90 sec. The barrier is significantly reduced as reaching 0.67 eV for I-V, 0.72 eV for C-V, 0.62 eV for IPE. From the
42
deposition time of 150 sec, the barrier is rather increased but still lower than the initial sample. When the deposition time is larger than 150 sec, the current is greatly reduced and capacitance is such a strange alteration that Barrier could not be extracted.
To explain the Schottky barrier height reduction, there are potentially three mechanisms, Fermi-level depinning by reducing the surface interaction, [59] formation/screening of dipoles at the dielectric/semiconductor interface, and reduction of fixed oxide charge. [60-62] Those are the results of the metal-insulator gap state. Additionally, Huang, L explain the mechanism of the Schottky barrier increase by the growth in the interface trap density. [63]
TABLE 7. Extracted Schottky barrier of Ni/AlN/4H-SiC by I-V, C-V, and IPE measurement with respect to the sputtering time of AlN.
Sample I-V Barrier (eV) C-V Barrier (eV) IPE Barrier (eV)
0 sec 1.710±0.013 1.746±0.006 1.600±0.006
30 sec 1.220±0.010 1.217±0.037 1.198±0.034
60 sec 1.113±0.014 1.089±0.014 1.003±0.012
90 sec 1.045±0.003 1.025±0.002 0.982±0.038
120 sec 1.048±0.014 1.026±0.021 1.003±0.017
150 sec 1.399±0.064 1.521±0.007 1.319±0.007
4.2.5 Transmission Electron Microscopy
Figure 31, Figure 32, and Figure 33 show the scanning transmission electron microscopy (STEM) cross sectional image of Ni/SiC junction. A sample with 1 min of deposition is used. Left image is bright field (BF), and right is annular dark field (ADF) image. The steps of SiC substrate is shown in the Figure 30. Figure 31 and Figure 32 show the very thin amorphous layer, which is expected to be oxide, aluminum, nitride layers. The thickness of layer is measured as 1.3 ~ 1.4 nm. Here, the energy dispersive spectroscopy shows the thin amorphous layer consists of aluminum and oxide layer. Aluminum and oxide are considered to be intermixed and the nitride is not detected by the energy dispersive spectroscopy.
43
Figure 31 Bright field (left) and annular dark field (ADF, right) STEM image of Ni/SiC junction with SiC surface steps.
Figure 32 Bright field (left) and annular dark field (ADF) STEM image of Ni/SiC junction with very thin interfacial layer.
44
Figure 33 Bright field (left) and annular dark field (ADF) STEM image of Ni/SiC junction in high resolution.
Figure 34 Energy dispersive spectroscopy of Ni/SiC junction.
45 4.3 Metal-insulator Gap State
The interfacial layer causes the significant reduction of Schottky barrier height. As mentioned in the previous chapter, the metal-insulator gap state is considered as the origin of the phenomenon. There have been reports about ultrathin insulators in between the metal and semiconductor can reduce Schottky barrier and contact resistance in Si [59, 64], Ge [65], and GaAs [66].
4.3.1 Fermi-level Depinning
Fermi-level pinning is a phenomenon that occurs in the interface of a semi-conductor in a metal- semiconductor function, which creates an energy barrier which is irrelevant to the work function of metal, and bends the conduction band and the valence band. From a technical standpoint, Fermi-level pinning creates a very big problem, which causes the Energy barrier to act as a parasitic resistance, dramatically reducing the performance of the transistors. Considering the pinning factor, the effective metal work function
M eff. is. (1 )
M eff S M S CNL
(16)where S is the pinning factor,
M is metal work function,
CNL is charge neutrality level of semiconductor. As the pinning factor is closer to the 1,
M eff. become closer to
M. The pinning factor of n-type 4H-SiC is known to be between 0.6 and 0.7, [6]As the thickness of amorphous layer is increased, the carrier transport mechanism originated to thermionic emission is significantly reduced, and the tunneling effect become dominant. This is consistent with the measurement results.
4.3.2 Screening of Interfacial Dipole
In the surface of 4H-SiC, there exist the spontaneous polarization originated in the anti-symmetry of wurtzite structure of 4H-SiC. The Schottky barrier is increased by the negative charge on the surface of the 4H-SiC, and as the distance between metal and semiconductor increased the effect of spontaneous polarization should be increased. [9] However, the amorphous layer which is consist with aluminum, nitride, oxide decreases the Schottky barrier. It is though that the dipole has formed inside the amorphous layer and suppress the effect of spontaneous polarization. [61, 64] There exist another possibility that the sputtering affected the edge of SiC surface and Si atom which is the origin of spontaneous polarization intermixed to amorphous layer so the spontaneous polarization decreased.
46
Figure 35 Brief energy band diagram for mechanism of Schottky barrier reduction by the Fermi-level depinning.
47 4.4 SiC MOSFET Structure
SiC MOSFET shows high performance in high voltage, high temperature, and high frequencies with low energy loss. SiC is large bandgap (~3.26 eV for 4H-SiC) semiconductor, and has high critical electric field, high saturation electron velocity, and high thermal conductivity. They are the reason that the SiC is expected to be next generation power MOSFET.
The reason that SiC has not been replaced the Si MOSFET is, however, SiC has serious degradation of the channel mobility, low stability of the threshold voltage, lower reliability of gate dielectric layers.
Most of those problems are originated in the initial surfaces of the SiC, and eventually, the quality between the oxide and SiC. The channel mobility of SiC devices (~3 cm2 V-1 s-1) have extremely low compared to the mobility of bulk SiC (950 cm2 V-1 s-1 for 4H-SiC) due to the SiO2/SiC interfacial defect.
[67, 68] The interface trap density (Dit) is two orders of magnitude higher than the case of the SiO2/Si.
The interfacial defects work as Coulomb scattering centers. Also, the hole mobility of SiC (100 cm2 V-
1 s-1) is much lower than the hole mobility of Si and also affected by the high interface trap density.
Therefore, most of the SiC MOSFET is limited for the n type of MOSFET.
There has been a lot of try to improve the quality of the SiO2/SiC interface and the established method is nitride passivation. [69-71] With an aid of the NO or N2O gas, the channel mobility was improved to 20 ~ 100 cm2 V-1 s-1. Interfacial nitrogen has reported to reduce the Dit. This is the standard process to enhance the interface between SiO2/SiC but requires very high temperature with toxic gas. The other option such as POCl3 which is reported recently also highly toxic. In order to overcome the interface defect between SiO2/SiC without the toxic process, there have also been other attempts replace the insulating material. N-containing insulator including SiN, is representative attempts and shows ~15 cm2 V-1 s-1until now, and still being actively research. [72]
48
Figure 36 Schematic diagram of Double-diffused metal-oxide-semiconductor field effect transistor (DMOSFET) and U-shaped metal-oxide-semiconductor field effect transistor (UMOSFET)
4.3.1 UMOSFET
Double-diffused metal-oxide-semiconductor field effect transistor (DMOSFET) and U-shaped metal- oxide-semiconductor field effect transistor (UMOSFET) are the representative structure of silicon carbide high-power field effect transistor. [73] For the both MOSFET, electron flow through vertically, via drift region and drain terminal. This vertical structure is advantageous in the high-voltage and high- frequency characteristics. For the DMOSFET, electron channel is formed laterally through inversion layer under the gate. UMOSFET uses the U-shaped gate which increases the cross-sectional area of the source-drain path, and this reduces the on resistance.
Figure 37 shows the process flows of UMOSFET fabrication. 4H high-doped SiC with n-/p-/n+ doped epi-layer is used as substrate. Using deep RIE, gate region is defined and insulator is deposited and etched. Figure 38 shows the example of structure and doping profile for UMOSFET. The Silvaco TCAD is used for the modelling. [74, 75] Substrate is n-type of 1×1019 cm-3, and the epi-layers are n-type of 1×1015 cm-3 for drift region, p-type of 1×1016 cm-3 for region with a graded doping density, and n-type of 1×1019 cm-3. As the bias is applied for the gate, electron can move through the channel as shown in Figure 39. Here, the interface trap density between oxide and SiC plays a significant role for
49 determining the threshold and the on-resistance.
Figure 37 Flow chart of UMOSFET fabrication processes.
50 Figure 38 Doping profile of representative UMOSFET
51
Figure 39 The simulation of electron flow as the gate bias is changed.
4.3.2 I-V Characteristic
Figure 40 and Figure 41 shows the drain current-drain voltage curve in accordance with the interface trap density. The interface trap density parameter is used as 1.25×1013 cm2 eV-1 in (Ec-0.06) eV to 1.16×1013 cm-2 eV-1 in (Ec-1.06) eV. [76, 77] 1.5×1015 traps/cm2 for 6H SiC, 1.0×1015 traps/cm2. Under the influence of a trap, the barrier shift is observed.
52
Figure 40 Id-Vd curve of without, and with the interface trap density of 1.25×1013 cm2 eV-1 in (Ec- 0.06) eV to 1.16×1013 cm-2 eV-11 in (Ec-1.06) eV in linear scale.
Figure 41 Id-Vd curve of without, and with the interface trap density of 1.25×1013 cm2 eV-1 in (Ec- 0.06) eV to 1.16×1013 cm-2 eV-11 in (Ec-1.06) eV in logarithm scale.
53
Figure 42 Id-Vg curve of without, and with the interface trap density of 1.25×1013 cm2 eV-1 in (Ec- 0.06) eV to 1.16×1013 cm-2 eV-11 in (Ec-1.06) eV in linear scale.
54
Appendix A Enhanced Plasmonic Welding of Silver Nanowire Junctions by Exerting Mechanical Compression during UV Irradiation
A.1 Silver Nanowires
It has been required to achieve high conductivity for the transparent electrode according to the great interest of variable optoelectronic devices such as touch screen panel, organic light-emitting diodes, and organic photovoltaics. [78-83] Over the past few decades, indium tin oxides (ITOs) has reigned over either research and industry for the field of optoelectronics due to the superior performance of both electrical and optical properties. [83, 84] However, not only the cost efficiency issues but also extreme reduction of conductivity with physical stresses such as bending and stretching are regarded as limitation. [85] There were various attempts to replace ITOs to overcome the restrictions of usage in stretchable and flexible devices. [80, 86] The candidates of the emergent transparent electrodes are conducting polymers, graphene, carbon nanotube, and metal nanowires. [87, 88]
Especially, the silver nanowires (AgNWs) are one of the most attracting materials due to their excellent electrical conductivity which is comparable to ITOs. [89] Silver that has exceptional electrical conductivity (6.3 × 10 S m ) gives high performance even when it used in nanowires as thin as diameter of several tens of nanometers which are almost invisible to the bare eyes. [81, 90-92]
Furthermore, AgNWs can be easily deposited by coating process while ITOs require sputtering and annealing processes. [87] Nonetheless, one challenging problem of AgNWs is contact resistance between the individual nanowires. The contact resistance between silver nanowire network is about
~GΩ sq . [93] Longer length of AgNWs, so called silver nanofibers, can be used to minimize the effect of contact resistance, but shorter length of AgNWs are advantageous to elevate the persistency of conductance in transform. [94] Therefore, it is very important to decrease the contact resistance to commercialize the AgNWs for the transparent electrode.