本论文 을을을을 Choi Deok-jun 의 Choi Deok-jun Choi Deok-jun 의의의 工学硕士 工学硕士论文 论文论文 로으OK 로으OK OK 함함함함 大学学院 韩国海军大学学院 韩国海事大学。韩国海事大学研究生院 研究生院 电子学研究生院。
This thesis proposes an adaptive turbo decoding algorithm for high-order modulation scheme combined with original design for a standard rate-1/2 turbo decoder for B/QPSK modulation. A transformation applied to the incoming I-channel and Q-channel symbols allows the use of an off-the-shelf B/QPSK turbo decoder without any modifications. To reduce the latency and power consumption, this thesis uses the combination of the radix-4, double-path processing, parallel decoding and early-stop algorithms.
This thesis implemented the proposed scheme on a field programmable gate array (FPGA) and compared its decoding speed with that of a conventional decoder. From the result of implementation, it is found that the decoding speed of proposed adaptive decoding is 6.4 times faster than that of conventional scheme under the following conditions: N = 212, iteration= 3, 8-states, 3 iterations and 8PSK modulation scheme.
Introduction
This thesis presents the need for a single turbo decoder to decode all modulation schemes so that it needs less hardware and less power consumption, and to reduce the cost of the receiver. A new decoding procedure allows the use of a turbo decoder originally designed for a standard 1/2 rate turbo decoder over B/QPSK modulation, to decode several keyed trellis modulation schemes over 2m-PSK/QAM constellations, with m ≥ 3. New turbo adaptive codes with two coded bits per symbol are based on rate realization.
Important issues in high-speed applications of turbo decoders are decoding delay and computational complexity. Like maximum a posteriori probability (MAP) decoding, iterative decoder recursively processes the received symbols to improve the reliability of each symbol based on constraints that. In the first iteration, the decoder uses only the channel output, and generates soft output for each symbol.
Therefore, the delay and complexity caused by several iterations and the high order of calculation, it may be difficult to implement decoding in hardware and apply high-speed wireless applications. To solve the delay problem, four decoding algorithms are presented in this thesis and combined into a decoder architecture such as radix-4, dual-path processing, parallel decoding and early stopping algorithms.
Adaptive Turbo Decoding Algorithm
Coset Symbol Transformer(CST)
To use the 1/2 rate turbo decoder, a transformation is applied such that the 8-PSK points are mapped to QPSK points labeled with .
Phase Sector Quantizer(PSQ)
After the turbo decoder evaluates the coded bits, the uncoded bit must be determined. Due to the structure of the turbo decoding algorithm, each decoder delays the data by a certain number of symbol periods. The phase information bits φ1, φ2, φ3 must be delayed by the amount of the turbo decoding delay to match the reconstructed code sequence.
Simulation Results
High Speed Turbo Decoder Algorithm
Parallel Decoding Algorithm
Unlike the original turbo decoder, consisting of two decoders connected in series, this thesis presents a parallel decoder structure that uses the parallel sum, where the two decoders work in parallel, updating each other immediately and simultaneously after each completes its decoding. When decoding the estimated data, this thesis uses the sum of the LLR outputs of the parallel decoders to reduce the latency by half while maintaining the same level of performance. The decoding iteration continues until a certain stop condition is met. Hard decisions are made based on the reliability measurements of the decoded symbol in the last decoding iteration.
The bit-error rate (BER) performance of the new fast adaptive turbo decoder architecture combining the four schemes is analyzed in this section. The performance of a high-speed decoder is almost the same as that of a conventional decoder. 4.1, this thesis proposes the adaptive turbo decoder architecture with a rate of 2/3 turbo-coded pragmatic TCM decoder using the off-the-shelf half-rate turbo decoder based on Fig.
Our decoder can support both half rate turbo decoder with BPSK modulation scheme and rate of 2/3 with 8PSK modulation scheme. A detailed signal flow of internal MAP based on high-speed algorithms is shown in Fig. The ALU (Arithmetic Logic Unit) calculates the extrinsic information using LLR outputs, the received symbol and the previous extrinsic information.
To add extrinsic information exactly in the next iteration, the decoder needs an ALU block with dual RAM ports (128x36). R4FBMu and R4BBMu calculate the branch metric for four samples of received data in both left-to-right and right-to-left directions simultaneously. Data computed from R4FSMu and R4BSMu are stored in 64x72 dual port memory.
Therefore, this thesis needs the two dual-port RAMs, which are R4FSM_RAM and R4BSM_RAM. 4.2(a) starts to calculate the external information and store external information in dual-port RAM with a size of 128x36 to input to the next iteration. addr bus Forward addr bus. Rx data bus Map2 data bus Map1 data bus. a) High speed turbo decoder architecture. b) Signal flow of internal MAP.
The Optimum Quantized Bits of the Adaptive Turbo Decoder … 28
The thesis designed an adaptive turbo decoder using VHDL (Very High Speed Hardware Description Language) and verified its performance through RTL simulation. Then, this thesis confirmed that the errors were corrected during processing in the RTL simulation. In the diploma thesis, a fast adaptive turbo decoder with 8-state, N=212, R = 2/3 and 8PSK modulation scheme is designed.
To compare the decoding speed of the conventional serial turbo decoder based on the radix-2 trellis structure. To compare the decoding speed between conventional and fast adaptive turbo decoder, this thesis implemented the conventional decoder using the same procedures. The maximum operational clock speed of the conventional and proposed decoders is 18[ns]. Table 4.2 shows a comparison of decoding speed between conventional and high-speed decoder.
In the case of combining the radix-4 and the parallel and dual-path process, the proposed high-speed decoder is 6.4 times faster than conventional decoders. This thesis presented the adaptive turbo decoding algorithm with two encoded bits per symbol, based on a realization of a rate n/(n+1) trellis encoded scheme using a standard turbo decoder. In this thesis, the adaptive high-speed turbo decoder was designed using the Xilinx chip (VIRTEX2P(XC2VP30-5FG676)).
그 결과, 제안한 디코더의 디코딩 속도는 기존 알고리즘에 비해 6.4배 빠른 것으로 나타났다. 사랑하는 사람들과 함께 학부, 대학원 생활을 마무리하면서 부족한 점이 많았을 때 제가 한 단계 도약할 수 있도록 도와주신 고마운 분들을 생각하게 됩니다. 먼저, 논문이 완성되기까지 언제나 따뜻하고 배려심이 많으시며, 밤새도록 미소를 지으며 낙심하지 않으시고 함께 해주신 정지원 교수님께 깊은 감사의 말씀을 전하고 싶습니다.
그리고 이제 사회에 첫 발을 내딛는 이 순간, 교수님과의 추억은 영화처럼 지나가고, 연구실, 체육관, 해외회의, 셀 수 없이 많은 맛있는 곳에서 함께 보낸 시간들에도 불구하고 레스토랑은 오래가지 못해요. 무엇과도 바꿀 수 없는 행복한 추억이고, 인생의 한 페이지를 넘기는 기분이에요. 또한 논문의 부족한 부분을 보완하고 알찬 내용으로 만들어주신 김기기 교수님, 윤영 교수님에게도 감사의 말씀을 전하고 싶습니다. 늘 새로운 가르침과 아낌없는 조언을 해주신 김동일, 조형래, 민경식, 강인호 교수님. 또한 감사합니다. 제가 연구실에 처음 입사했을 때 항상 친동생처럼 보살펴주시고, 지금도 제 고민을 들어주시는 태길 선생님께 감사의 말씀을 전하고 싶습니다. 멀리 일본에 계신 성준님께도 감사의 말씀을 전하고 싶습니다.
이제 대전 연구소에서 저를 응원해주고 함께 좋은 추억을 만들 수 있게 도와준 친구 인기에게 고마운 마음을 전하고 싶습니다. 언제나 내 곁에 있어주고, 지금은 멀리 있지만, 언제나 내 마음 속에 있는 자랑스러운 친구 석봉이와 승재, 그리고 98년 모든 학우들에게 감사의 인사를 전하고 싶습니다.
