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Digital Logic Design

Naehyuck Chang Dept. of EECS/CSE

Seoul National University 4190.201.001

2010 Spring Semester

L P L E mbedded L ow- P ower L aboratory Supplementary Slide for the lab

(2)

ELPL

Embedded Low-Power Laboratory

Logic Tester

Detect high and low

Share the same power supply

Share the reference voltage, i.e., GND

2

Circuit under

test Power

supply

+

!

Logic tester

! + Probe

Tuesday, March 23, 2010

(3)

CMOS Logic Gates

Threshold voltage of MOSFETs

GND

VT of NMOS VT of PMOS VDD

Gate is destroyed Gate is destroyed

Logic 1

Logic 0

Not allowed for steady state NMOS on

PMOS on

(4)

ELPL

Embedded Low-Power Laboratory

Logic Tester

Detect high

Should have no loading effect

Detect low

Should have no loading effect

How current sink for the LED drive?

Output impedance

4

220

220 74LS04

74HCT04

Tuesday, March 23, 2010

(5)

Diode (1)

P-N junction diode

1N4148

(6)

ELPL

Embedded Low-Power Laboratory

Diode (2)

Ideal diode

Forward bias: V1 > V2 Reverse bias: V1 < V2

V1 V2

Tuesday, March 23, 2010

(7)

Diode (4)

Real diode

Break down

Silicon Diode

Germanium

Diode

(8)

ELPL

Embedded Low-Power Laboratory

Logic Tester

Prevent from floating

Can we combine these together?

8

220

100K

220

100K

Tuesday, March 23, 2010

(9)

Diode (6)

Diode in digital circuits

Silicon Diode: switching and rectification Germanium Diode: detection

(10)

ELPL

Embedded Low-Power Laboratory

Logic Tester

Final design

10

220

220

100K100K

High Low

Tuesday, March 23, 2010

Referensi

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