In addition, the calibration loop for the frequency response of the TP-FPSC provides an additional suppression to the in-band phase noise of the output signal. Norm of implementations of this work and state-of-the-art ring-VCO-based ILCMs.
List of Tables
Introduction
Motivation
Despite the high frequency, the proposed frequency calibrator can correct fVCO drifts and requires low power without using high frequency circuits. It was the first calibrator to calibrate real-time fVCO offsets in the mm-wave band with extremely low power consumption of less than 1 mW.
S REF Pulse S INJ VCO S OUT Gen
This versatile calibrator can remove three main causes of feRRs, especially the first-time slope modulation calibration caused by injection.
S INJ S OUT
Dissertation Organization
Prior ILCMs with Real-Time Frequency Calibration
ILCMs with a PLL-Based Frequency Calibrator
S REF PLL V CONT S OUT
S INJ
Pulse Gen. Timing Control
ILCMs with a Frequency Calibrator Using a Replica-VCO or a Replica-Cell-Based Delay Line
FLL Pulse Gen
Replica VCO
S REF
S OUT
Replica- Delay Cells
Pulse Gen
V CONT S REF
Divided control voltage, VCONT, instead introduces the noise of the replica VCO into the in-band noise of the output signal in the ILCM. Finally, this structure suffers from the problems that the VCO consumes twice the power, while the noise of the VCO is doubled.
ILCMs with a Period-Detector-Based Calibrator
Period ACC detector
S OUT Comp
Period detector
T VCO
N ∙ T VCO T REF
T REF
T ERR
Second, since TERR is very small compared to TREF, the frequency error detection gain is small. This small detection gain makes these structures more sensitive to the noise of the loop components.
ILCMs with a Frequency Calibrator Detecting Phase Shift
Phase-Shift Detector Using a TDC
ACCCorr
S OUT TDC
T VCO T VCO +Δ T VCO T VCO +Δ
Phase-Shift Detector Using a Pulse Gating Technique
When the injection pulse is closed, the accumulated phase error of the VCO is not rearranged and maintains the phase error, and the PD can thus detect the ∆φ and frequency shift error. Since the calibration bandwidth of fERR and phase error is slow, this calibrator does not effectively remove VCO jitter noise.
LFPulse Gen
However, if the injection pulse is closed often to extend the calibration bandwidth, the effect of the injection will be reduced and the overall noise may also worsen. Second, the periodic gating of injection could generate in-band spurs, which degrade the noise performance of the ILCM.
S OUT PD
First, the noise reduction effect of the VCO due to the calibrator is reduced because the calibration is only possible when the injection pulse is gated, and not every time.
Gated Pulse
Phase-Shift Detector Using Delay Cells
2.6(a), the delay cells delay SOUT by the coasting period of the VCO, TVCO, and generate a delayed signal from SOUT, SOUT_D. However, the accuracy of the ∆ϕ shift detection can be degraded by the delay error of delay cells and the input shift of the PD, so the additional offset calibration is crucial.
2.6(b), because the delay cells receive the signal from the VCO before injection and delay it, they can preserve the intrinsic phase information of the VCO without the effect of the injection. In addition, the calibrator can detect a ∆ϕ shift at each reference period, so the frequency calibration bandwidth can be wide enough to suppress the flicker noise of the VCO.
S OUT ϕ OUT
Then PD compares the phase difference between SOUT and SOUT_D and the shift ∆ϕ can be detected. Since this method can detect fERR with a simple structure, it requires low power and small silicon area.
An Ultra-Low Power and Compact LC-Tank-Based Frequency Tripler
Depending on the choice of fLC, the proposed architecture can be implemented as a frequency multiplier with an arbitrary multiplication factor.
![Figure 3.1. Frequency triplers: (a) conventional self-mixing architecture [35] (b) proposed architecture](https://thumb-ap.123doks.com/thumbv2/123dokinfo/10487155.0/28.892.250.636.283.958/figure-frequency-triplers-conventional-mixing-architecture-proposed-architecture.webp)
Circuit Designs
3.4, the spur level was significantly reduced with a D-to-S amplifier that eliminated the AM interference. Reference bumps at the outputs of the LC-resonator and the D-to-S amplifier, (VO+ – VO–) and VOUT, respectively.
Measurement Results
The excitation level was minimized when the third harmonic of fREF was close to the resonant frequency of the LC tank, but increased as fREF deviated. The difference between the two phase noise curves was very close to 9.5 dB (20·log 3dB), which is the theoretical limit.
Discussion
A Low-IPN mm-Wave
Injection-Locked Frequency Multiplier for 5G
Another important advantage of the proposed architecture is that it can support backward compatibility. Section 4.3 presents the concept and design of the proposed FTL and ILFM.
Limits of Prior Frequency-Tracking-Loop Architectures for mm- Wave ILFMs
To overcome the problem of excessive power usage of calibration circuits for mm-wave ILFMs, the architecture in [57] presents an FTL using an envelope detector, as shown in Fig. However, wrapper tracking provides almost no additional information once injection lock is obtained.
Proposed ILFM With an Ultra-Low-Power FTL Using the Averages of the Phase Deviations
- Overall Architecture
- V-to-I Amplifier and the QVCO
- Quadrature Generator, the Pulse Generator, and the Switched RC- filters filters
- Coarse Frequency Selector
- Static Frequency Offset by Mismatch Effects in the FTL
The transfer function of HUP(jω) in (1) represents the upconversion of the injection signal noise to the output. 4.9(b) shows that the total phase noise is dominated by the noise from the injection clock.
Power Consumption (mW)
4.15(b) shows the variation of the phase noise at the same deviations, when fOUT is swept by changing fINJ. No reported power consumption of only the ILFM (total power including 20 GHz PLL is 137 mW).
Background Calibrator
The orthogonal mechanisms for the generation of these three causes of fERR and the limits of the capacity of conventional calibrators are explained in detail in Section 5.2. It can eliminate all three causes that generate fERRs accurately, since the proposed TP-FPSC provides three orthogonal calibration mechanisms, and thus the ILCM becomes able to minimize the level of the reference trace.
Analysis on Frequency Error Generation Mechanisms of Root Causes and Limits of Conventional Calibrators
Three Root Causes of Frequency Errors and Limits of Conventional Calibrators Calibrators
S REF Pulse S INJ S OUT
Calibrator:Freq. Drift
Slope Modulation ΔSL f DF :Phase Offset ɸ OS
In this case, the calibrator reacts as if this phase error was generated due to fDF, even though it was actually caused by ϕOS. Because of this confusion, the calibrator will tune fVCO to reduce the phase error, and the end result will be the generation of fERR.
Frequency Drift f DF
These systematic errors of the conventional frequency calibrators leave a residual fERR, which generates the second cause, namely the phase offset, ϕOS. In particular, in the case of using the calibrator in [29], the error in the delay time of the delay line, which also varies due to supply and temperature variations, and the input offsets of the PD cause ϕOS.
Delay Line
Frequency Drift (f DF )
6fDF∝ϕPD[1]5
3Phase realignment
Phase Offset
1SREF
Phase Offset (ϕ OS )
DTCPD
Replica- Delay Cell
Slope Modulation
Slope Modulation (ΔSL)
2f ERR
3SLINJ > SL NO-INJ
Removing ΔSL by calibrator causes f ERR (b)
S OUTPG
DCDL (T VCO )
Edge Sel
How Slope Modulation Generates Phase Error and thus Frequency Error Error
However, when SLINJ is greater than SLNO-INJ, the magnitude of the current of D2 increases when the slope of the leading edge of SO,1 is steeper, causing the falling edge of SO,2 to fall faster. Due to the reduction of the delay of D2, the total delay time of the inverter chain becomes less than 4τ0.
When SLINJ is equal to SLNO-INJ, the total delay time after passing the four delay cells is 4τ0 at SO.5, since injecting SINJ does not change the delay of the second converter D2 (ie, still τ0). In this simulation, fDF and ϕOS were assumed to be zero (i.e. only the slope effect.
5.7(b), although the change in transducer slope fades out at SO.5 after passing through the transducer chain, the change in propagation delay remains as a static phase shift. 5.8(a) shows the simulation result of the amount of phase shift in different ratios of SLINJ to SLNO-INJ.
SL INJ = SL NO-INJ
5.7(a) shows that SINJ with a variable SLINJ is injected into a ring VCO consisting of five delay cells, each of which has unit delay, τ0. On the contrary, when SLINJ is smaller than SLNO-INJ, the reduced current of D2 makes the falling edge slower and lengthens the delay.
5.8(b) shows the simulation result of the reference track level under the same conditions as Figure 4(b). The red dotted line represents the reference trace level in a conventional calibrator that can remove fDF.
According to the simulation, the absolute value of the phase shift increased almost linearly as the ratio between SLINJ and SLNO-INJ deviated from unity, and this result was in good agreement with the analysis in [83]. 4(a) were applied without the use of calibrators. As the ratio of SLINJ to SLNO-INJ deviated from unity, the level of the reference trace increased, along a logarithmic line. In Fig.
ILCM Using the Proposed Background TP-FPSC
Overall Architecture of the ILCM with the Background TP-FPSC
TP-FPSC
The MVG includes three D-flip-flops (DFFs) to sample PDOUT from PD sequentially at different times, so that three independent sets of information can be derived from the same output, i.e., PDOUT. Unlike conventional charge pumps, the pulse width of the PSUD is fixed so that the digital information from the BBPD is accumulated in CLj in a discrete manner.
Pulser
Following this notation, PDOUT is sequentially sampled at FE1, FE4, and FE2 by the three DFFs in the MVG, generating three corresponding one-bit error codes, DER1, DER2, and DER3, respectively. Each of these three error codes, DERj, goes into the j. analog accumulator (A-ACC) and determines whether charges will be drawn to or extracted from the loop capacitor CLj.
Multi-V C GeneratorVCDL
It then supplies the MVG with its one-bit output, PDOUT, with the polarity information of ϕPD. While typical digital accumulators, to achieve high resolution, require a large number of bits or a delta-sigma modulator (DSM), the proposed A-ACC can easily improve the resolution by simply reducing the pulse width of PSUD.
BBPD − SVCDL
Three Error Detection Mechanisms of the TP-FPSC
S REF S OUT
PD OUT DN X X
5.11(a) shows how to detect the frequency drift, when fVCO is higher than N·fREF so that fERR is positive, while τVCDL is 2TVCO and SLINJ is SNO-INJ. In this situation, ϕPD becomes constant for all rising edges of SOUT and SVCDL, since τVCDL deviates from 2TVCO due to any static errors of the frequency calibrator.
XSREF
5.11(a) – (c) show how these three causes of fERR, i.e. the frequency drift, the phase shift and the slope modulation, can be detected at PDOUT. In this case, the effect of the frequency drift of fVCO appears in ϕPD, when the first rising edges of SOUT and SVCDL or the second rising edges of SOUT and SVCDL are compared by the PD.
X X XFE2
Settling Behaviors of Three Calibrations of the TP-FPSC
The frequency calibration bandwidth was designed to be ten times larger than the phase shift calibration bandwidth. Since the bandwidths of the three calibration loops were designed so differently, the proposed architecture can ensure stability.
Time (μs)
To ensure the stability, we designed each bandwidth of the three calibration loops differently, resulting in different deposition velocities of VC1, VC2, and VC3. The bandwidth of the slope calibration is designed to be one-tenth of that of the phase-offset calibration.
V C1 :Freq. control
However, their effects would be mixed with each other in real situations and the three calibrations would proceed simultaneously. 5.12, the frequency calibration is completed in less than 10 μs, so the ILCM can start generating the accurate output frequency in a very short time.
V C2 :Phase-offset controlVC3 :Slope control
At this moment, SOUT can already have an ultra-low jitter, but it cannot yet have a low reference trace, because the other two main causes of fERR. After the establishment of VC3, finally, the ILCM can achieve both a low reference incentive and a low jitter.
Design of Sub-Building Blocks: Slope Controller, VCO, and VCDL
S INJSlope Controller
IN VCO OUT
C BANK2 COARSE 2
Buffer
5.15(b) shows the spectrum when two functions of TP-FPSC, viz. frequency calibration and phase shift calibration, were enabled so that the level of the reference trace was reduced to -64 dBc. 5.15(d) shows the measured spectrum of the 2.5-GHz output signal when all three functions of the TP-FPSC were turned on.
Output Buffer
5.15(a) shows the spectrum, when all three functions of the TP-FPSC were completely turned off. The frequency of the VCO was manually adjusted to achieve the injection lock.) In this situation, the output signal of the ILCM was prone to all three causes of the frequency error; thus the measured level of the reference track was as high as about -33 dBc. Finally, when all three functions, including the slope calibration, were turned on, all three main causes of the frequency error were removed, and the level of the reference trace was reduced to -72 dBc, as shown in Fig.
VCDLSlope
Controller Coarse-Tune
Circuit BBPD &
Input Buffer
33.5dBc
100MHz2.4GHz
64dBc
100MHz+5-5
72.4dBc
Calibration
Since the injection lock mechanism had a very wide bandwidth when the reference clock was injected, the phase noise of the ring VCO was strongly suppressed at both frequencies. When the TP-FPSC was turned on, the wide bandwidth of the frequency calibration provided an additional suppression of the in-band phase noise of the VCO, so that the ILCM was able to achieve ultra-low jitter.
Output Frequency (GHz)
72.9dBc
100MHz
Output frequency = 2.4GHz, Jitter RMS = 136.0fs
Free-running VCO TP-FPSC off
TP-FPSC on
Offset Frequency (Hz)
Output frequency = 2.5GHz, Jitter RMS = 135.8fs
FoM JIT (dB)
Spur (dBc)
The comparison table shows that the ILCM in this work can achieve not only the lowest RMS jitter but also the lowest reference spurt by using the proposed TP-FPSC; This is how it achieved the excellent FoMJIT. In this work, we presented a VCO-based ILCM with low jitter and ultra-low reference spurring.
Conclusion
As a result, the ILCM in this work can achieve and maintain low reference boost and low RMS-jitter while using a small amount of power and a compact silicon area.
Cho, “A fully digital clock generator using a fractional injection-locked oscillator in 65 nm CMOS,” in IEEE Int. Hsieh, “A divider-less sub-harmonic injection-locked PLL with self-adaptive injection timing,” in IEEE Int.
Acknowledgments
Publications
Choi, “A PVT-robust and low-jitter ring VCO-based injection-locked clock multiplier with a continuous frequency tracking loop using a replica delay cell and a double-edge phase detector,” IEEE J. Choi, “ A 185-fsrms integrated jitter and -245dB FOM PVT robust ring- VCO-based injection-locked clock multiplier with a continuous frequency-following loop using a replica delay cell and a double-edge phase detector,” IEEE International Solid-State Circu Conference (ISSCC), Feb.
![Fig. 2.6 shows a frequency calibrator using delay cells to detect f ERR [29] – [31]. As shown in Fig](https://thumb-ap.123doks.com/thumbv2/123dokinfo/10487155.0/26.892.172.716.184.783/shows-frequency-calibrator-using-delay-cells-detect-shown.webp)
