Introduction …
Motivation and relative works
Thesis contribution
When the source side becomes larger than that of the nominal, as shown in Fig. Initially, the effects of the fin body thickness variations on Ion and Ioff are analyzed.
Impact of Fin Body Thickness (T si ) Variation and Leakage Optimization of 32-nm FinFET …
Model for fin body variation in the 32 nm FinFET
The Figure 2-1 shows the 3D structure of dual gate SOI FinFET devices with a fin body structure. Tsi is the fin body thickness, and Tʹsi is the variation in the fin body width.
TCAD results of fin variation FinFET
These analyzes show that source-side Tsi variations are considered to have a significant effect on the electrical operating properties of the DC device. As summarized in Table 2-2, in nFinFET, Ion is reduced by 1% and Ioff is only half that of the nominal device when the source-side Tsi is 20% greater than the nominal thickness (i.e., Sb, source Tsi is 12 nm). Thus, as either the source-side or the drain-side Tsi become narrower than nominal, both Ion and Ioff increase.
However, as Tsi on either the source or drain side becomes thicker than the nominal value, both Ion and Ioff decrease. From this analysis, we can expect a FinFET structure with a large rib on the source side and a small rib on the drain side to achieve a reduced Ioff. Therefore, increasing the fin body size on the source side is structurally simple and its performance is reasonable.
Therefore, a simple threshold voltage variation model is used for ion and Ioff changes due to Tsi variation.
Doping effect of the fin body variation FinFET
However, in practice, Ioff decreases more and more while Ion does not increase, due to the increasingly large depletion region and Vth. These changes of current distribution show a consistent relationship and it can be expressed numerically. Therefore, a simple model of the variation of the threshold voltage is used for the changes of Ion and Ioff due to the variation of Tsi. a) Nominal (b) Sb and (c).
Threshold voltage variation model
Nb, Xdep, and Cox are the body doping, channel depletion width below the gate, and gate capacitance, respectively [33]. Furthermore, in the FinFET, the value of Xdep is reduced by half due to the fin body thickness Tsi variation [34]. For this reason, a new threshold stress model is designed by the variation of Tsi of the fin body.
The minimum Tsi is considered for the calculation of the void width, because the fin body has a non-uniform thickness. 2-2, both Ion and Ioff decrease, and therefore, this behavior is modeled using the increase in threshold voltage. Comparison of Vth values obtained from TCAD results and proposed models against different source-side Tsi (a) nFinFET and (b) pFinFET.
As can be seen from this graph, there are non-linear features in the Vth for the smaller Tsi and larger Tsi cases.
On and leakage current model
Comparison of Ion values obtained from TCAD results and proposed models against various source-side Tsi (a) nFinFET and (b) pFinFET. The Ion simulation results agree well with the results of the proposed models for various source-side fin thicknesses as shown in Figure 2-6 (a) and (b). As shown in figure 2-5 and equation (2.2), the threshold voltage in the large source side Tsi case is increased due to the variation in Tsi.
However, Tsi on the source side exceeds that of the nominal by 10%, there is only a 30% leakage reduction. It states that when the source-side Tsi is less than nominal, the leakage current increases exponentially. This change in leakage is attributed to the reduction of the threshold voltage on the side of the small source.
Comparison of Ioff values obtained from TCAD results and proposed models versus different Tsi (a) nFinFET and (b) pFinFET on the source side.
Performance metrics
In this thesis, the effects of fin body variations on inverter performance are analyzed by modulating Vth of FinFET using BSIM models. The proposed variation of fin FinFET can achieve 32% leakage reduction with 1% increase in delay by comparing the performance of the inverter with larger source-side structure to that of the nominal filament body. The inverters are simulated by varying the source-side thickness from 10% to 20%, with the drain-side thickness kept at 10 nm to analyze the impact of Tsi variations on circuit performance and energy savings.
On the x-axis, the label (i.e. n10 and p10) indicates a 10% increase in the thickness of the source side of the inverter for both nFinFET and pFinFET devices. 2-9, the 10% increase in source-side thickness for both n- and p-type FinFETs achieves the highest leakage reduction sensitivity over the delay. When comparing the second and third data points, increasing the thickness of the pFinFET source side instead of nFinFET is effective in reducing leakage.
Therefore, it is concluded that leakage reduction along with a reasonable delay penalty is achieved by keeping the rib width variation less than 10% compared to the nominal structure and that changing the pFinFET source side shape is more effective in reducing leakage.
Leakage optimization
Capacitance change analysis is performed for rib pitch and height variation in a 32nm single-gate FinFET. Increasing the height of the fin (H-fin) results in an increase in the capacitive circuit and the total gate capacitance. Since the overall width of a single fin FinFET is determined by the fin height (Hfin), a discrete number of multi-fin structures are then used to create wider (or more powerful) devices.
And the electrical parameters of the multifins FinFET are calibrated with BSIM FinFET models [31]. This change can be explained by the reduction of the coupling capacitance as Pfin increases. The electrical characteristics of multi-fin FinFET with different fin pitches and fin heights are simulated using TCAD.
An increase in Pfin also results in a decrease in coupling capacitance (Cc) and total gate capacitance (Cg_total).
Simple and accurate modeling of multi-fin coupling capacitance in 32nm FinFET
Model for multi-fin single gate FinFET
The device structure of the 32 nm single gate multi-terminal FinFET used in this thesis is shown in Figure 3-1. Hfin, Pfin, Tsi, and Lg are fin height, thread height, fin thickness, and gate channel length, respectively. Fin height (Pfin) is determined by the center-to-center distance between two fins.
And, the height of fin (Pfin) is set to its minimum value which is limited by the lithography resolution [41]. Narrow gate thickness (Tsi) is required to reduce the short channel effect and the leakage current can be reduced by the improved controllability for the gate. Therefore, an accurate understanding of not only the DC current variation but also the dynamic behavior (e.g., gate capacitance) of the multi-wire FinFET is required.
Capacitance of the multi-fins FinFET
The driving current increases in the multiple fins, but the capacitive coupling effects between adjacent fins will occur. FinFET structure font representation with three fins and single gate indicating the gate-to-source and drain capacitance (Cgs, Cgd). Each capacitance component is extracted for three-fin, one-gate FinFET using AC small-signal analysis.
The junction capacitance model parameters can be used to predict the transfer and input characteristics of the transistors, making the proposed models very useful for circuit design [42]. Therefore, by using two geometrical parameters (i.e., Pfin and Hfin), the simple coupling capacitance models are proposed, which can be useful to explain the multifin-related effect in capacitance.
Capacitance model for fin pitch (P fin ) and fin height (H fin ) variation FinFET
Comparison of Cg_total values between TCAD simulations and proposed models for different fin pitches (Pfin). In this figure, fin pitch is increased, Cc is reduced, but Cgs and Cgd are no change. For example, when Pfin is doubled from 40 nm to 80 nm, Cc is reduced up to 70%, and then the FinFET has 8% less Cg_total.
As the fin height increases, Cgd becomes 3 times larger and Cgd increases 5 times. For example, when Hfin increases from 10 nm to 100 nm, Cc becomes 8 times larger and Cg_total becomes 6 times larger. Comparison of Cc values between TCAD simulations and proposed models for different fin heights (Hfin).
3-10, increasing the fin height results in an increase in total capacity due to the significant increase in coupling effects between tall fins.
Input capacitance and FO4 delay for fin variation FinFET
Change of inverter input cap and FO4_delay values obtained from SPICE simulations for different fin heights (Pfin). Change of inverter input limit and FO4_delay values obtained from SPICE simulations for different fin heights (Hfin). Figure 3-12 shows the change of input capacitance and FO4 delay for different Hfin.
From section 3-2 we understand that as the height of the fin (Hfin) increases, the Cc and the total input capacitance increase. For example, when the fin height increases from 10 nm to 100 nm, the input capacitance increases up to 9 times and the FO4 slows down to 4 times. Therefore, the FO4 delay of FinFET inverter is better when using the minimum fin height (Hfin).
Delay and area sensitivity by P fin changes
The electrical characteristics of the SOI double-gate FinFET with different body thicknesses on the source and drain sides are simulated using TCAD. The proposed models agree well with the simulation results, with errors less than 1.3% in Ion and 4.8% in Ioff. The results indicate that there are significant docking effects when the pitch (Pfin) and height (Hfin) of the fin change in the multiple fin structure.
The results indicate that the capacitance and delay of the inverter are significantly affected by the Pfin and Hfin variations. 2010, 'Identification of bottlenecks to the RF performance of FinFETs', in International Conference on VLSI Design, pp.111-116. 2012, 'Comparative robustness of geometry-dependent capacitances of planar FETs and dual-gate FinFETs: optimization and process variation', in VLSI-TSA symposium, April, pp.1-2.
2006, 'Dependence of FinFET RF performance on fin width', in Topical meeting SMIC in RF Systems, January 2009, 'Measurement and analysis of parasitic capacitance in FinFETs with high-k dielectric and metal-gate stack', in International Conference on VLSI Design, Jan. 2003, 'Leakage Current Mechanisms and Techniques for Reducing Leakage in Deep Micrometer CMOS Circuits', in IEEE Proceedings, pp.305-327.
Conclusion and Summary
