In analog LDOs, we discuss advanced techniques such as local positive feedback loop and zero path that can improve stability and PSRR performance. In analog-digital hybrid LDOs, to achieve both fast transient and high PSRR performance in a fully integrated chip, how to optimally combine analog and digital LDOs is considered based on the characteristics of each LDO type.
Technical Terms and Abbreviations
INTRODUCTION
As shown at the top of Figure 1, the battery provides charges at the inputs of the DC/DC converters, and these converters supply supply voltages to the loads that contain the charges in the capacitors (CL, DC/DC) as the desired voltage level. Additionally, loads can operate optimally at their own supply voltage level, but DC/DC converters only provide the same voltage level to their loads.
Battery
We put forward the future work of LDO in Section IV and draw conclusions in Section V.
DC/DCDC/DC
CPU Camera
VCO Memory
ADCCL,DC/DC
ADCLDO
LDO LDO
FUNDAMENTALS OF LOW-DROPOUT REGULATORS (LDOS) 2.1 BASIC OF LDOS
- Operation of LDOs
In the second step, feedback loop works to regulate MP current (IOUT) as same value of IL, and restore VOUT same value with reference voltage (VREF). For example, as shown in the top of Figure 3, when IL changes from minimum IL (IL, min) to maximum IL (IL, max), the current from CL (ICL) initially compensates IL, and this causes VOUT decrease.
V REF
This increase of |VGS| of MP leads to a large increase of IOUT, so MP can supply current in the same amount with IL, thus putting VOUT at almost the same value with VREF. As shown at the bottom of Figure 3, when ICL initially compensates IL, VOUT decreases, but as the portion of IOUT compensation increases, VOUT.
V OUT
As shown in Figure 2, analog LDOs basically consist of a P-type pass transistor (MP), an error amplifier (EA) and a load capacitor (CL). Then the negative feedback loop kicks in: the input difference of EA decreases as VOUT decreases and the reduction is amplified with EA gain (AEA), which induces a huge decrease in the gate junction voltage (VG) of MP.
I OUT
V OUT @load transientIL
I CL I OUT
Because VG must be greater than the sum of VOUT and threshold voltage (Vth) of MN. PSRR is the ratio of the change in VIN to the change in VOUT it produces. If VIN fluctuates, in MN case, VOUT is robust to VIN fluctuations, since in view of VOUT, only the drain of MN fluctuates, and the MOSFET is inherently robust to the change of VDS.
Briefly, after determining the type of pass transistor, EA type should be selected since the way vR cannot be represented in VOUT [2]. In MN case, since low 1/gm impedance of MN is seen by VOUT, 𝜔P,OUT can easily be higher than 𝜔P,G and makes LDO gate pole dominant (GPD).
LDO with M N
As mentioned in Section 2.1.2, in the path related to the first term of (1), vR is multiplied by gm in the MP case, and multiplied by 1/ro in the MN case. In the MP case, increasing Cgs (between VG and VIN) helps to improve PSRR performance and in the MN case, increasing Cgs (between VG and VOUT) helps to improve PSRR performance. Briefly, to maximize vR to VG swing, PMOS mirror can be selected as it delivers the current affecting VG in the same direction of resistive distribution path.
It is worth noting that the aforementioned techniques are only used to improve the PSRR in the low frequency band. BW–3dB PSRR (p1) may be more important than PSRRDC in the case where a high-frequency stimulus is injected into the VIN, such as optical receiver applications [4].
Small signal model
If the frequency over –3dB bandwidth (BW–3dB) of loop which is 𝜔P,G, AEA is reduced and PSRR performance is degraded. In OPD LDO case the PSR is kept constant as the load impedance does not just roll off AEA. Returning to the GPD LDO case, if the frequency is over the unity gain frequency (UGF), there is no more gain from EA, so the PSRR is kept constant.
If the frequency is above the output pole, the load impedance decreases, so the PSRR increases. If the frequency is above BW–3dB of the load impedance generated by CL and the equivalent series resistance (RESR) of CL, the load impedance remains constant, so the PSRR is constant.
PSRR =
Load Transient Response Time (T R ) & Settling Time (T S )
Then the feedback loop operates at the speed of the loop bandwidth, and since IOUT can then supply the same amount of current with IL, VOUT can be the same with VREF. TR is defined as the time for the changed VOUT to compensate and move toward the desired value. In Figure 10, (7) and (8), the calculation of TR is introduced according to the relationship between TR and IL transition time (Tedge), where t0 is the moment when IL changes [7].
TS is defined as the time that VOUT deviating from VREF returns close to VREF, typically entering the range of 2% error with VREF.
Dropout Voltage (V DO ) & Quiescent Current (I Q )
I IN I OUT IN OUT
The solution is to let the parameters affecting stability change adaptively as the 𝜔P,OUT changes. So, at IL,min, the LDO can maintain stability without reducing the BW in heavy load condition. In [10], by dividing EA into EA' and a small amplifier amplifier, isolates the large output resistance of EA (ROUT,EA) from the large total capacitance of MP seen from gate (Cgg).
In addition, for reduced gain due to EA' (AEA'), the small gain amplifier compensates the gain as AEA/AEA' to make the overall DC gain the same as conventional EA. Thus, the LDO can maintain stability by splitting the large resistance and capacitance without additional power consumption to push 𝜔P,G away.
Loop Gain [dB]
Small gain amplifier
DESIGN AND SIMULATIONS OF AN ANALOG LDO 3.1 DESIGN OF AN ANALOG LDO
The PSRR state comes from DC/DC converter which supplies the voltage to the LDO with 100mVP-P switching ripple and 50kHz switching frequency. To make the power of the LDO less than 10% of the load power, VDO is chosen as 200mV. In deciding the EA structure, we chose 1-phase NMOS input PMOS mirror differential to single-ended EA for simplicity as shown in Figure 17 .
To increase gm,EA and expand the output dynamic range, we increased the width of transistors.
V OUT,EA
SIMULATIONS OF AN ANALOG LDO
Using an iprobe, we investigated the open-loop gain and phase of the total system as shown in Figure 21. By injecting AC signals to the supply, we found the PSR across frequency as shown in Figure 22.
Load cont. V B
If we need more gain in the low VIN condition, as shown in Figure 23, a two-stage amplifier with a local positive feedback loop topology can be used that makes ROUT of PMOS part of the first stage, ideally infinity using negative gm [11] . However, if the W/L ratio of PMOSs in the positive feedback loop is larger than that of diode-connected PMOSs in the first stage, locking may occur. This means that the output cannot be appropriately changed by the input as the gm of local positive feedback transistors becomes larger than the gm of input transistors.
We can add a null path between the power supply and the MP gate, as shown in Figure 24 [12]. At this location, the LDO transfer function can add a zero to remove the pole of the stage 1 output node using the Pole Zero Elimination (PZC) technique.
Local positive feedback
Zero path
FUTURE WORK
- MOTIVATION OF DIGITAL LDOS
As shown in Figure 25, basic digital LDOs consist of a comparator (COMP), a switching controller (SWC), and MPs that turn on and off completely. Since MPs can provide large current operating in the triode region, digital LDOs are also becoming popular in memory loads that produce large ILs.
NVREFCODE
COMP
In digital LDO stability, since the SWC is usually an accumulator that is a discrete-time integrator, it contains a pole at z=1 in the z domain, digital LDOs naturally classified as GPD LDOs [14]. However, depending on the value of FS, this system may be unstable causing limit cycle oscillations. The digital LDO in [13] mentioned earlier can also solve the stability problem by causing the FS to slow down when the value enters the settling range.
In terms of power and area, OPD LDOs have a power-area trade-off for protecting PM, GPD LDOs do not need to increase IG, but need to supply static power to EA, and also do not need large CL, but the MP size must be larger than digital LDO as MP must operate in the saturation region. Furthermore, the VDO of digital LDO can be small, only about 50 mV, operating in the triode region.
Event occurs
CODE
DIGITAL LDOS FOR FAST TRANSIENT AND HIGH ACCURACY
For digital loads, if VOUT droop is greater than the logic threshold value, it can generate critical errors in operation. Thus, in the frequently changing IL with the change of the logic levels, the preservation of VOUT hang is one of the most important goals in digital loads. Moreover, little decrease in VOUT which is the supply of the logic gates slows down the speed of calculation of digital logic.
If we want to compensate the current in several cycles regardless of FS speed, ADC is needed as it can expect the amount of change of IL. However, depending on the level number of the ADC, there is a trade-off between resolution and power and area.
HYBRID LDOS FOR FAST TRANSIENT AND HIGH PSRR
EA +MP,AVG
CONCLUSIONS
Choosing the appropriate pass transistor type, EA and dominant pole along with the applications is critical in LDO design. In analog LDOs, we deal with advanced techniques such as local positive feedback loop and zero path which improves the stability and performance of PSRR. ADC-based voltage comparators for TS improvement have an ambiguous answer to the problem that one ΔVOUT information contains many solutions about ΔIL.
In analog-digital hybrid LDOs, for both analog and digital loads in a fully integrated chip, a GPD+digital LDO combination is preferable to an OPD+digital combination with moderate PSRR performance and high accuracy. In addition, the slow TR needs to be improved due to the stability problem in the GPD LDO and the clock-dependent bias in the digital LDO.
Kwon, “A 0.9 V 60 μW 1-bit fourth-order delta-sigma modulator with 83 dB dynamic range,” IEEE Journal of Solid-State Circuits, vol. Raychowdhury, “All-digital controller with low dropout, adaptive control and reduced dynamic stability for digital load circuits,” IEEE Transactions on Power Electronics, vol. Mercier, “A low dropout recursive digital voltage regulator with successive approximations, PD compensation and sub-LSB load control,” IEEE Journal of Solid-State Circuits, vol.
Choi, "A 320μV-Output Ripple and 90ns- Settling Time at 0,5V Supply Digital-Analog-Hybrid LDO Using Multi-Level Gate- Voltage Generator and Fast-Decision PD Detector," IEEE European Solid State Circuits Conference, vol. Raychowdhury, "Switched-Mode-Control Based Hybrid LDO for Fine-Grain Power Management of Digital Load Circuits," IEEE Journal of Solid-State Circuits, vol.
ACKNOWLEDGEMENTS
