We report theoretical studies on the thickness-dependent electronic properties of PdSe2 and their effects on PdSe2 field-effect transistors through experimental demonstrations. This gate-tunable rectification in PdSe2 heterojunction field-effect transistors can be understood by analyzing the alignment of energy band diagrams. Small gating and semi-p-type characteristics are observed. a) Calculated on/off ratio values from transfer IV curves for uniform thickness PdSe2 field effect transistors.
Introduction
Results and Discussion
Crystal Structures of Monolayer and Bulk PdSe 2
Two-dimensional materials with pleated pentagonal structure are highly desirable two-dimensional materials due to the low symmetry lattice structure. Primitive unit cell of monolayer PdSe2 is rectangular with the in-plane lattice constant as = ~5.6 Å, ay = ~5.9 Å and the vertical ripple distance d = ~1.6 Å. The vertical distance between two monolayers is ~4 Å and the unit cell of bulk PdSe2 is orthorhombic unit cell.
Electronic band structure of monolayer PdSe2 is calculated and plotted along the highly symmetric path for the 1st Brillouin Zone (BZ), X-G-S-Y-G path in Figure 1c. Therefore, the electronic band structure of the specific path of the 1st Brillouin Zone is not enough, and energy contour plots of the lowest conduction band and the highest valence band of the entire 1st Brillouin Zone are required to understand the electron and hole carriers in monolayer PdSe2.
Band Structures of PdSe 2
The band gap values for monolayer to pentalayer and bulk PdSe2 are calculated via DFT using GGA and PBE functionals. There are other studies reporting different band gap values, especially a zero band gap for bulk PdSe2. We experimentally verified that bulk PdSe2 has a non-zero band gap, and this is discussed in the next section on electrical measurements.
Uniform Thickness PdSe 2 Field Effect Transistors
Optical microscope images for the devices and atomic force microscope images for PdSe2 flakes with the height profile on the black or white line in the AFM image are provided with the I-V transfer curves. As the thickness of the PdSe2 flame increases, from Figure 3a to Figure 3d, the on and off current increases and the on/off ratio decreases. In general, the channel resistance is inversely proportional to the channel thickness, so the On and Off currents should be proportional to the channel thickness if the channel material is a normal material.
However, since PdSe2 has decreasing band gap as material thickness increases, sharply rising current level can be seen from Figure 3a to Figure 3d. If PdSe2 flake thickness is thin enough, n-type characteristics can be seen as I-V curves in Figure 3a. Since 100 layers of two-dimensional material can be considered as a bulk material, these experimental results indicate a non-zero band gap in bulk PdSe2, which is consistent with the non-zero band gap value in bulk in Figure 2d.
On/Off Ratio and Maximum Mobility Distribution
Device Structure and Output I-V Curves of PdSe 2 Heterostructure Field Effect Transistor
Device Structure and Output I-V Curves of PdSe2 Heterostructure Field Effect Transistor (Device 1). a) OM and AFM images for Device 1. Heterostructure PdSe2 flake is used as channel. When VGS is negative near -80 V, the current level at negative VDS is higher than the current level with positive VDS. However, with positive VDS, the current is relatively low and does not increase even though VDS is continuously increasing.
It is easier to see the rectification behavior in the linear scale IV curves in the inset of Figure 5c. On the other hand, the IV curves for the positive VGS also show rectification, as we can see in Figure 5d. An interesting finding is that this current rectification direction is completely reversed when VGS is positive.
This current rectification behavior is also more easily seen in the linear scale I-V curves in the inset of Figure 5d. This PdSe2 heterostructure field effect transistor shows rectification behavior, and the rectification direction can be controlled by the VGS, which has great merit compared to the other reported gate-tunable diode device [22].
Energy Band Diagram Analysis on Gate-Tunable Rectification
Thermionic emission of small holes and thermionic emission of small electrons and tunnel current from drains contribute to the total current. Therefore, the total current amount is minimized, and current level in BD3 case is the smallest among BD1~BD4 case current level. Another thing than the BD2 case, however, is that the BD3 case is slowly increasing.
Therefore, BD3 sheath current is not perfectly saturated and increases slowly as VDS magnitude increases for the negative voltage direction. Since there is a large energy barrier for holes, only small hole thermionic emission contributes to the total current. At the source side, since there is a small energy barrier for electron current, relatively large electron flow contributes to the total current.
Therefore, the BD4 region in Figure 5d shows a higher current level than the current of the BD3 case. Because this second energy barrier is thinned by the high VGS, electrons from the source can tunnel through the barrier to drain.
Rectification Ratio in PdSe 2 Heterostructure Field Effect Transistor (Device 1)
The rectification ratio becomes the highest value when VGS is -40 V and a further increase in VGS results in a decrease in the rectification ratio. The increase in VGS results in bending of the energy band in the BD1 and BD2 band diagram in Figure 5e. From -40 V to -80 V for VGS, since the increase share in the total current is higher in the case of BD2, the rectification ratio becomes the highest when VGS is ~40 V.
When VGS is positive from 10 V to 80 V, the current rectification ratio curve appears monotonically increasing as VGS increases. It is also found that the correction ratio value when VGS is positive is generally higher than the case when VGS is negative. The rectification ratio becomes more than 100 when VGS is ~80 V, but the rectification ratio is just over 10 when the VGS range is between -40 V and -80 V.
Therefore, this large difference between the two reverse currents in BD2 and BD3 causes the difference in the order of the value of the rectification ratio in Figure 6. Thus, using the analysis of the energy band diagram in Figure 5, we can understand that the reason why the curve of the rectification ratio in Figure 6 shows the curve of the rectification ratio, which varies with the VGS gate voltage.
Transfer I-V Curves of PdSe 2 Heterostructure Field Effect Transistor (Device 1)
Since these transfer I-V curves in Figure 7c have clear Down current at positive VGS, the I-V curves can be said to be semi-p-type. In the transfer I-V curves in Figure 7d, the electron current when VGS is positive is higher than the current when VGS is negative. If limited VGS range is changed to a more proper range, such as from -10 V to 20 V, the transfer curves show clear Off state.
Although the electron current is increasing in the negative VGS range, since the current level in the positive VGS is higher, it can be considered as a semi-n-type characteristic. From Figure 7c,d, a single PdSe2 heterostructure field-effect transistor can be n-type or p-type transistor. By changing VDS, the I-V transfer curves can be changed to n- or p-type, which means that the PdSe2 heterostructure can be used to realize n- or p-type transistors.
Flat Region in Transfer I-V Curves and Energy Band Diagram Analysis (Device 1)
When VGS is negative, the electron current is almost negligible and there is a small energy barrier for holes at the drain, resulting in a relatively high current at BD1 in Figure 8b. When VGS is ~0 V, the current is minimized as there are sufficient energy barriers for holes and electrons, respectively, which is confirmed by BD2 in Fig. 8b. However, the degree of band bending is different for thick and thin regions of PdSe2 flakes.
If VGS is less than ~10 V, electron thermionic emission current in source is mainly controlled by the height of conduction band in thin PdSe2 flake which gradually decreases for increasing VGS. Now, as we further increase VGS, energy band in thin PdSe2 flake moves down, but the energy band at the heterojunction does not change much, as the energy band in thick PdSe2 flake remains almost the same. As a result, as total current is slowly increased, the flat region appears when VGS is between ~10 V and ~30 V.
However, if VGS is higher than 30 V, the energy band bending in the thin flame becomes substantial and the tunneling barrier in the heterojunction thins, thereby increasing the electron tunneling current as seen in Figure 8c BD5. Using this analysis of the power band diagram extension, it is understood why there is a flat region in the I-V transfer curve when VDS is 0.1 V and VGS is between ∼10 V and ∼30 V.
Device Structure and Output I-V Curves of PdSe 2 Heterostructure Field Effect Transistor
We refer again to the data from the other study in Figure 5b for information on the energy band of PdSe2 [23]. Using the energy values such as CBM, VBM and band gap sizes, the four energy band diagrams are plotted in Figure 9d. In the case of BD1 in Figure 9d, the electron flow is negligible as there is a large energy barrier for electrons at the drain.
But, according to BD1 and BD2 in Figure 9D, as there is a difference between energy barrier size for holes, there should be difference in the amount of hole stream between BD1 casing and BD2 casing. Therefore, the energy band diagram analysis agrees with the measured output I-V curves in Figure 9b. In BD3 band diagram in Figure 9D, as there are relatively large energy barriers for both electrons and holes, total stream level is smaller than the current level in Figure 9B.
In the BD4 band diagram in Figure 9d, since there are also relatively large energy barriers for electrons and holes respectively, the total current level is less than the current level in Figure 9b. Since the energy barrier for electrons on the source side in BD4 is lower and thinner than the energy barrier for electrons on the BD3 drainage side, the highest level of current is observed in the BD4 region compared to the current level in the BD3 region in figure 9c.
Transfer I-V Curves of PdSe 2 Heterostructure Field Effect Transistor (Device 2)
Conclusion
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