CERTIFICATION OF APPROVAL

INTRODUCTION

Research Rationale

Problem Statement

Objectives

Scope of Study

LITERATURE REVIEW

Duty Cycle

Effects on Gate Driver
Effects on Buck Converter
Effects on Vout and lou 1

Pulse Width Modulation (PWM)
Body Diode Conduction
Buck Converter

Operation Mode of Buck Converter

Smaller duty cycle changes affect gate driver operation, converter application, and pulse width modulation. Whereas the pulse width of M1 will increase as the duty cycle of the gate driver increases. The gate driver duty cycle is applied to the resulting power MOSFET, M3, giving a new duty cycle to buck converter.

This means that the duty cycle of the converter is based on the output of the power MOSFET, M3. This equation can be implemented using buck converter as shown in Figure 4. With a constant value of V;., v •• can be varied depending on the duty cycle applied to the gate driver. Vout is low when Dis is low. 2), the gate operator can function even at a lower duty cycle.

So by varying the PWM at the gate driver, it will also vary the duty cycle. The resulting power MOSFET, M3 from the gate driver acts as the switch of the buck converter.

Figure 2: Conventional Gate Driver (CGD)

METHODOLOGY

Project Planning
Project Activities

Construction of the PWM

CGD's Construction
RGD's Construction
Other's Part Measurement

Node Voltage Output
ResultantPowerMOSFET,M3

Buck Converter's Application

lout and Vou 1 at Lower Duty Cycle

Many research papers are collected to understand the basic concept related to duty cycle of the high frequency gate driver. The analyzes in the impact of duty cycle on the gate driver will be discussed in detail in Chapter 4. However, the PWM's setting is not a constant value as the different value of duty cycle must be applied.

Therefore, in section 4.1.1, the pulse width at PWMJ and PWM2 at different duty cycles tested in the simulation will be shown. The node voltage is measured at 23.5% of duty cycle at Ml for COD and ROD. Also, the same graph will be analyzed for different value of duty cycle for 1 both drivers.

Changes to the duty cycle in the gate driver Ml will affect the duty cycle in M3. Therefore, the construction of the buck converter will be based on the duty cycle in M3. This duty cycle in M3 can be obtained from the duty cycle of the gate driver, Ml.

In addition, iL performance can be evaluated based on different values of duty cycles applied to the driver according to the duty cycle changes in MI. If the step-down converter operates in DCM, a low duty cycle can be specified for the high-frequency gate driver. So in order to get the duty cycle value at M3, a driver simulation needs to be done.

The MOSFET's resultant power plot is then measured to obtain the duty cycle value. The low duty cycle for the high-frequency gate driver can be obtained from the inverter's operating mode, V output and lout characteristics. This value is checked for all circuits in this project, which includes different duty cycle values.

RESULT AND DISCUSSION

Results

Pulse Width Modulation (PWM)
Conventional Gate Driver (CGD)

Resonant Gate Driver (RGD)

Maximum Value for£,

Buck Converter's Performance

Inductor Current (iL) Operation Mode

I •• , and v •• , at 16% Duty Cycle for CGD
loutand V..,,at 15%DutyCycleforRGD
V aut for CGD and RGD
lout for CGD and RGD

The tone duration shown at PWMJ represents the duty cycle of the gate driver at 235 us. Therefore, a summary of the PWM settings for various duty cycle values is shown in Table 8 below;. Thus, a change in pulse width will result in a different duty cycle value for the high-frequency gate driver.

In this situation, every change to the duty cycle at Ml will change the duty cycle at M3 as shown in Table 10. This is because the final value of lower duty cycle can be obtained from the buck converter's performance which is shown in section 4.1.4. Moreover, the different value of duty cycle applied to the driver will also affect the body diode conduction time for 15 ns dead time.

Any change in the duty cycle of a high frequency gate driver will affect the duty cycle at M3. Then the ROD duty cycle will be varied to get a different value of the driver duty cycle. When the duty cycle at Ml is reduced, the duty cycle at M3 will be reduced.

This is because the fmal duty cycle value obtained from the inverter converter performance will be discussed in Section 4.1.4. A different value of the duty cycle at M3, as mentioned in sections 4.1.2.3 and 4.1.3.4, will affect the operation of the value converter. From the duty cycle value, all components of the buck converter can be calculated by referring to Eq.

Since the duty cycle in M3 for CGD and RGD is different, the value for the buck converter components will also be affected. ILave for the buck to RGD converter decreases when the duty cycle is decreasing as shown in Table 17 above. Thus, 15% duty cycle in CGD and 14% in RGD are not suitable for the gate driver to operate the buck converter.

Thus, the lou~ and V-out-for-buck converter will be directed to this M3 duty cycle. In addition, the different duty cycle at M3 will affect the value of L and C for the buck converter.

Table 8: PWM's setting for Different Value of Duty Cycle

CONCLUSION AND RECOMMENDATION

Conclusion

Throughout this project, two types of gate drivers have been used to drive the buck converter, namely CGD and RGD. Both drivers must operate at a low duty cycle to see the impact on the driver and buck converter. For example, it has been determined that the lowest duty cycle of a CGD is 16% and 15% for RGD.

When both gate drivers operate below these values, the buck converter begins to operate in DCM. For each change of duty cycle at Ml by a gate operator, it will result in another duty cycle at M3.

Recommendation

Yahaya, “Analysis of Proposed High Frequency Resonant Gate Driver for a New SRBC Circuit with Soft Switches,” PhD. Jain “A novel pulse resonant MOSFET gate driver with efficient energy recovery” in IEEE Power Electron. Pan and P.K Jain, "A New Resonant Gate Driver with Two Half Bridge Structures for Both Top Switch and Bottom Switch," Queen's University Department of Electrical and Computer Engineering, Canada.

Steve, "Predictive Gate Drive Boosts Synchronous DC/DC Power Converter Efficiency," Texas Instruments Incoprated, April 2003. The layout improvements introduced greatly improve the Ron* range value while keeping the device at the forefront of slew rate, gate charge and robustness. I so Source-drain Current lsoM (2) Source-drain Current (pulsating). see test circuit, Figure 5) IRRM Reverse Recovery Current.