DECLARATION OF ORIGINALITY

The development of this project will begin with the design of the CDC unit and the asynchronous FIFO block after reviewing the technologies available for CDC circuit design. The internal sub-blocks of the asynchronous FIFO block will be modeled using Verilog HDL before being integrated into higher block levels.

CHAPTER 6 VERIFICATION SPECIFICATION AND SIMULATION RESULTS

Test Plan for Asynchronous FIFO Block’s Functional Test

• Testbench Program for CDC Unit’s Integration Test (Test for SPI Part)

Micro-architecture of the CDC low to high speed unit Schematic diagram of a synchronizer block. Simulation result for test case #1 using Modelsim Simulation result for test case #2 using Modelsim Simulation result for test case #3 using Modelsim Simulation result for test case #4 using Modelsim with (focus on SPI data output).

LIST OF TABLES

LIST OF ABBREVIATIONS

Introduction

• Background Information
• MIPS (Microprocessor without Interlocked Pipeline Stages)
• UART (Universal Asynchronous Receiver Transmitter)
• Clock Domain Crossing
• Problem Statement and Motivation .1 Problem Statement
• Motivation
• Objectives
• Project Scope
• Contributions
• Report Organization

Next, test benches will be developed to functionally check the design specification of the CDC device and its internal blocks (CDC design). Chapter 4 shows a functional and structural view of the RISC32 containing the CDC circuit.

Figure 1.1.1-F1: 5-stage pipeline execution

Literature Review

• RISC32 Architecture
• I/O System in RISC32 Processor
• UART Part
• SPI Part
• GPIO Part
• Related Info of Metastability Problem .1 Metastability
• Synchronizer
• Available Solutions for Passing Numerous CDC Signals
• Multi-Cycle Path (MCP) Formulation
• FIFO Implementation Strategies
• Synchronizing Counters for FIFO Pointer Design .1 Binary Counter
• Gray Code Counters

One of the most important techniques when using a Multi-Cycle Path formulation is to transfer the activation signal, recognized as an acknowledgment signal, back to the clock domain of the transmitting side, as shown in Figure 2.4.1.1-F1. In Figure 2.4.1.2-F1, the clock domain of the receiving side has a finite state machine that sends a legal signal to the accepting side when data is legal in the data register entry.

Figure 2.1-F2: 5-stage pipeline processor microarchitecture [8]

System Methodology/Approach

Design Specifications

• Methodology and General Work Procedures
• Flow of RTL Design
• Micro-architecture Specification
• RTL Modeling and Verification
• Logic Synthesis for FPGA
• Design Tools
• ModelSim Intel FPFA Starter Edition 2020.1
• Xilinx Vivado Design Suite
• Technologies Involved .1 FPGA
• System performance definition

The CDC device and the asynchronous FIFO block internal design will be described in the microarchitecture specification. RTL coding on the CDC device and the asynchronous FIFO block can begin after the development of the microarchitecture specification. If the design of the CDC unit and the asynchronous FIFO block is found to not meet the specified functional requirements, especially its time requirements and functional correctness during the development of the project, then it is necessary to repeat the design flow.

Finally, in this project, logic synthesis will be performed using FPGA technology after successfully meeting the specified functional requirements of the developed RTL models. The CDC circuit model will be said to be well prepared for logic synthesis once its functionality is successfully verified. According to the result of the logic synthesis, the gate-level netlist is again checked for functional correctness.

FPGA or Field Programmable Gate Array technology will eventually be used for the logic synthesis of the CDC unit and the asynchronous FIFO block.

Table 3.1.2-T1: Comparison between simulation tools

Implementation Issues and Challenges

Timeline

• FYP I Gantt Chart
• FYP II Gantt Chart

System Specification

• RISC32 Pipeline Processor System Overview .1 Architecture of RISC32 Pipeline Processor
• RISC32 Pipeline Processor’s Structural View
• RISC32 Pipeline Processor’s Memory Map
• RISC32 Pipeline Processor’s Chip Interface
• RISC32 Pipeline Processor’s Input Pin Description
• RISC32 Pipeline Processor’s Output Pin Description
• RISC32 Pipeline Processor’s Input Output Pin Description

The RISC32 5-stage pipelined processor under development contains five hardware stages which are IF (instruction fetch), ID (instruction decode and operand fetch), EX (execute), MEM (memory access) and WB (write back) stages. Thus, it will take five clock cycles for each instruction to pass through all five stages to complete its execution.

Figure 4.1.1-F1: Functional overview on the architecture of RISC32 (including CDC circuit)

Micro-Architecture Specification

• CDC High to Low Speed Unit (Micro-Architecture Specification) .1 CDC High to Low Speed Unit’s Functionality/Feature
• CDC High to Low Speed Unit’s Input Pin Description
• CDC High to Low Speed Unit’s Output Pin Description
• Signals Being Applied the CDC High to Low Frequency Synchronization in RISC32 The CDC for high to low frequency synchronization in RISC32 is applied to the original input
• Micro-Architecture of the CDC High to Low Speed Unit (Block Level)
• Explanation of CDC High to Low Speed Unit Design Specification
• N-bit Asynchronous FIFO block
• N-bit Asynchronous FIFO block’s Functionality/Feature
• N-bit Asynchronous FIFO Block Interface
• N-bit asynchronous FIFO block’s Input Pin Description
• N-bit asynchronous FIFO block’s Output Pin Description
• Design Partitioning of the N-bit asynchronous FIFO block
• N-bit FIFO Memory Block
• N-bit FIFO Memory Block’s Functionality/Feature
• N-bit FIFO Memory Block Interface
• N-bit FIFO Memory Block’s Input Pin Description
• N-bit FIFO memory block’s Output Pin
• Gray Code Counter
• Gray Code Counter’s Functionality/Feature
• Schematic Diagram of Gray Code Counter
• CDC Low to High Speed Unit (Micro-Architecture Specification) .1 CDC Low to High Speed Unit’s Functionality/Feature
• CDC Low to High Speed Unit’s Input Pin Description
• CDC Low to High Speed Unit’s Output Pin Description
• Signals Being Applied the CDC Low to High Frequency Synchronization in RISC32 The CDC for low to high frequency synchronization in RISC32 is applied to the original output
• Explanation of CDC Low to High Speed Unit Design Specification
• Micro-Architecture of the CDC Low to High Speed Unit (Block Level)
• Synchronizer Block (Micro-Architecture Specification) .1 Synchronizer Block’s Functionality/Feature
• N-bit Synchronizer Block’s Input Pin Description
• N-bit Synchronizer Block’s Output Pin Description
• Clock Divider Block (Micro-Architecture Specification)
• Clock Divider Unit Interface
• Clock Divider Unit’s Input Pin Description
• Clock Divider Block’s Output Pin Description

Because the asynchronous FIFO block inside the high-to-low CDC unit will temporarily store data before it is read, the size of the address width of the FIFO memory, which will represent the depth of the memory space, must be large enough to prevent the FIFO memory from filling up quickly. The basic internal design of an asynchronous FIFO block will be designed as shown in Figure 3.2.3.1-F1. An overview of the block-level partitioning of an N-bit asynchronous block FIFO is in Figure 5.2.5-F1, and their connections are as shown in Figure 5.2.1-F1, while the details of its internal blocks are shown in Table 5.2.5-F1.

Its count value represents the address of the current position of the memory to be written. The count value represents the address of the current position of the memory to be read. The Gray code counter is logic circuit used to count the address of the target memory position in the FIFO memory block using gray code.

An overview of the designed CDC low to high speed device characteristics is given below.

Figure 5.1.5-F1: Micro-architecture of the CDC high to low speed unit

Verification Specification and Simulation Results

Simulation Results of Verification Testing of Asynchronous FIFO Block

Test case 2: When the reset signal went low, tb_boasynfifo_empty_wr and tb_boasynfifo_empty_wr were declared, which means the FIFO is empty for writing and reading. Tb_boasynfifo_almostfull_wr is asserted after tb_biasynfifo_syn_wraddrgray_rd is manually incremented to represent the real state to which the address value will increment when data is successfully written. Test case 4: Tb_boasynfifo_full_wr was asserted after tb_biasynfifo_syn_wraddrgray_rd was manually increased.

Test case 5: The tb_biasynfifo_en_rd being attached causes the tb_boasynfifo_addrgray_rd to increase, meaning new data is being read, which is 3.

Test Plan for CDC High to Low Speed Unit’s Functional Test

Simulation Results of Verification Testing of CDC High to Low Speed Unit

Test Plan for CDC Low to High Speed Unit’s Functional Test

Its function to generate asserted data when two similar asserted values ​​are detected for two consecutive cycles of I/O clock (tb_uicdc_l2h_ioclk).

Simulation Results of Verification Testing of CDC Low to High Speed Unit

Wait for output of synchronized data and single-cycle data. tb_uicdc_l2h_ioclk, and then becomes 5'b00000 for the rest of those cycles and also remains in . Then, it also successfully detected that there are two similar asserted values ​​for tb_uiclk_l2h_syn_din for two consecutive cycles of tb_uicdc_l2h_ioclk and produced another single-cycle long asserted output (uocdc_l2h_singlecycle_dout) for the second cycle of tb_icdcllk_2. Test Case 5: The positive edge of the input data (tb_uiclk_l2h_syn_din) was again successfully detected and produced a long asserted single-cycle output (uocdc_l2h_singlecycle_dout) for the first cycle of tb_uicdc_l2h_ioclk.

Then it also successfully detected that there are several similar asserted values ​​for tb_uiclk_l2h_syn_din for three consecutive cycles of tb_uicdc_l2h_ioclk and asserted single cycle long output (uocdc_l2h_singlecycle_dout) for the second and third cycle of ctl_ulk_h.

Test Plan for CDC Unit’s Integration Test with RISC32

• Testbench Program for CDC Unit’s Integration Test (Test for UART Part)
• Testbench Program for CDC Unit’s Integration Test (Test for SPI Part)

Since the original baud generator block inside the UART controller runs on the system clock which is 100 MHz and will divide it into 20 MHz before generating the required battery rate according to the operation structure shown in Figure 6.7-F3, so it is modified in this project to remove the part that will divide the frequency already connected to 100 MHz into 100 MHz. Hz instead of 100 MHz. Configure the UARTCR register in crisc (under test) to enable the UART and set the baud rate. Configure SPI in crisc (under test) by clearing SPISR, enabling RXBHE, setting SPITX data and setting SPICR to enable SPI, set it as master and set the SPI clock speed.

Keep running the SPI in crisc (under test) until the data is sent over SPI and received by itself. Configure the SPI in the crisc (under test) by clearing SPISR, enabling RXFHE, setting the SPITX data and setting SPICR to enable SPI, set it as master and set the SPI clock rate. This is the Verilog test bench program used to make UART say "HELLO WORLD!" to PC with a baud rate of 9600.

This is the Verilog test bench program used to make the RISC32 send A to Z over SPI at a frequency of 2 Hz.

Figure 6.7-F2: Connection mechanism for CDC unit’s integration test with RISC32 to test for SPI part

Simulation Results of the CDC Unit’s Integration Test with RISC32

• Test Case #1: Sending “HELLO WORLD!” through UART before Integration
• Test Case #2: Sending “HELLO WORLD!” through UART after Integration
• Test Case #3: Sending A to Z through SPI before Integration
• Test Case #4: Sending A to Z through SPI after Integration

The data "HELLO WORLD!" is successfully received by crisc (acting as client) bit by bit and can be found in brx_fifo_data_in from brx of UART_controller from crisc (acting as client). The time taken by the UART to start sending the data is recorded as 2.3x109 ps and this will be used to compare with the time taken after integration of the CDC unit in RISC32. The time taken by the UART to start sending the data is recorded as 10.3x109 ps and it is found to be much longer than the time taken before integration.

This is because the time taken is extended due to the slower I/O clock connected to the I/O. The data "A" is successfully received by crisc (acting as client) bit by bit and can be found in brx_fifo_data_in of brx of UART_controller of crisc (acting as client). The time it takes for the SPI to start sending the data is recorded as 2.3x109 ps and this will be used to compare with the time it takes after integration of the CDC unit in RISC32.

The time it takes for the SPI to transmit the data is recorded as 10.3 x 109 ps, while the time it takes for the UART to transmit the received SPI data is recorded as 51.1 x 109 ps and is found to be much longer than the time it took before integration.

Figure 6.9.2-F1: Simulation result for test case #2 using Modelsim

Conclusion and Recommendation

• Conclusion
• Future Work and Recommendation
• Testbench for Asynchronous FIFO Block’s Functional Test
• Testbench for CDC High to Low Speed Unit’s Functional Test
• Testbench for CDC Low to High Speed Unit’s Functional Test

Therefore, some alternative ways can be used to minimize the size of the used memory or solve this problem. For example, the design of the CDC circuit can be changed so that only the usable input data is stored in the FIFO memory, so that the size of the memory used can be minimized. Mehra, Design and Verification Serial Peripheral Interface (SPI) Protocol for Low Power Applications, 2014. https://www.infineon.com/dgdl/Infineon-Universal_Asynchronous_Receiver_Transmitter-Software+Module+Datasheets-v05_03-.

EN.pdf?fileId=8ac78c8c7d0d8da4017d0fae8ffb2012&utm_source=cypress&utm_medium=r eferral&utm_campaign=202110_globe_en_all_integration-files. https://www.rs-online.com/designspark/spi-communication-and-common-issues. 2020) "An Energy-Efficient FPGA Partial Reconfiguration-Based Microarchitectural Technique for IoT Applications", Microprocessors and Microsystems [Online], vol. Test Case 2: Write data in and wait for data out. posedge tb_uicdc_h2l_sysclk, tb_uicdc_h2l_ioclk) $stop;. Test case 4: Data in for similar asserted value detection case repeat (2)@(posedge tb_uicdc_l2h_ioclk) begin.

Test Case 5: Start repeating case of detecting similar asserted values ​​(3)@(posedge tb_uicdc_l2h_ioclk). posedge tb_uicdc_l2h_sysclk, tb_uicdc_l2h_ioclk) $stop;.

FINAL YEAR PROJECT WEEKLY REPORT

• WORK DONE
• WORK TO BE DONE
• PROBLEMS ENCOUNTERED
• SELF EVALUATION OF THE PROGRESS

It was determined that the design of the CDC unit was not correct and caused a number of errors and an undesired result. Subsequently, the design of the CDC unit was modified and now the result of the integration tests for UART was as expected. Necessary to thoroughly understand the operation of the IO system, so that the problem in the design of the CDC unit can be easily solved.

Diagrams for CDC unit microarchitecture and structural view of RISC32 with integrated CDC should be drawn. The previously drawn diagrams for the microarchitecture of the CDC unit and the structural view of the RISC32 are not quite good and had to be redrawn. More effort was required to ensure the completeness of the written FYP2 report.

The microarchitecture diagram of the CDC unit and structural view of RISC32 is drawn.

UNIVERSITI TUNKU ABDUL RAHMAN