LIST OF ABBREVIATIONS
CHAPTER 2 Literature Review
2.4 Available Solutions for Passing Numerous CDC Signals
In order to solve the problems related to passing multiple CDC signals [11], the FIFO techniques and Multi-Cycle Path (MCP) formulations are good ways to use. Among these available solutions for passing multiple CDC signals, the asynchronous FIFO implementation is the most recommended one and it is easy to implement.
It is provided two types of Multi-Cycle Path (MCP) formulations which are able to solve metastability problem:
Closed-loop Multi-Cycle Path formulation with feedback
Closed-loop Multi-Cycle Path formulation with acknowledge feedback
It is also provided two types of FIFO techniques which can act as closed-loop approaches for metastability problem:
Using of Asynchronous FIFO
Using of 2-deep FIFO
2.4.1 Multi-Cycle Path (MCP) Formulation
The use of Multi-Cycle Path formulation is a basic strategy for transferring numerous CDC signals safely. It refers to transmitting an asynchronized data to another clock domain according to the control or enable signal that is synchronized. The data and control signal will be sent together at the same time to allow the data to be set up on the register’s inputs of the destination whereas the mentioned control signal will be synchronized for two clock cycles of the receiving side before arriving at the register’s load input of the destination [11].
Advantages:
The appropriate pulse width is not necessary to be calculated by the sending clock domain before sending between the different clock domains.
The clock domain of the sending side is only needed to input an enable signal into the clock domain of the receiving side in order to indicate that data is prepared to be loaded in which the enable signal has no need to be sent back to its original logic circuit.
This method will pass numerous CDC signals without synchronizing them and will pass a enable signal which has been synchronized to the clock domain of the accepting side at the same time. The clock domain of the receiving side will not sample the received CDC signals until the enable signal is successfully synchronized before arriving at the destination register.
This strategy is actually known as MCP Formulation due to its properties that the asynchronous data will be transferred directly to the destination clock domain and held for certain numbers of clock cycles of the receiving side which allows the synchronization of an enable signal and get the signal into the destination clock domain before allowing the asynchronous data to alter.
Since the asynchronous data is transferred and held stable for numerous clock cycles before it is sampled, there will be no risk that the value being sampled to become metastable already.
2.4.1.1 Closed-loop Multi-Cycle Path Formulation with Feedback
One of the significant techniques in using a Multi-Cycle Path formulation is transferring the enable signal which will be recognized as an acknowledge signal back to the clock domain of the sending side as shown in Figure 2.4.1.1-F1.
Figure 2.4.1.1-F1: Multi-Cycle Path (MCP) formulation with acknowledge [11]
In Figure 2.4.1.1-F1, the acknowledge feedback signal produces a pulse of acknowledge which is used as input data to a finite state machine block that will generate a ready signal to show that it is okay to alter the value of input data again now. When the signal (aready) becomes asserted, the transmitter will be free to transfer new data as well as the accompanying control signal (asend). This can be said as a feedback path that is automatic and is always assuming that the clock domain of the receiving side will always be prepared for the next data to be synchronized through the Multi-Cycle Path formulation [11].
2.4.1.2 Closed-loop - Multi-Cycle Path Formulation with Acknowledge Feedback
It is a variation of the technique described in section 2.4.1.1 which is fully responsive and uses a Multi-Cycle Path formulation is to transfer the enable signal back to the transmitting clock domain as the acknowledge signal. As shown in Figure 2.4.1.2-F1, it will only be done after the destination clock domain acknowledges the acceptance of the data by using a pulse (bload).
Figure 2.4.1.2-F1: MCP formulation with ready-ack [11]
In Figure 2.4.1.2-F1, the clock domain of the receiving side has a finite state machine that transmits a legal signal to the accepting side when data is legal on the data register’s input. This data will not be actually loaded until the receiving side’s logic approves that the data could be
loaded by making the signal (bload) to be asserted. There will be no feedback to the transmitting clock domain until the data is successfully loaded, then the acknowledge signal (b_ack) will be transferred back in a similar way as the Multi-Cycle Path formulation with automatic feedback.
It can be said as a feedback path that requires the action on the logic of the clock domain of the receiving side before capturing the data and sending the feedback [11].
2.4.2 FIFO Implementation Strategies
2.4.2.1 Passing Numerous Bits CDC Signal Using Asynchronous FIFOS
Transferring multi-bit data can be done using an asynchronous FIFO. It is normally a register buffer or shared memory that allows data to be input from the clock domain of the writing side into it and allows the data to be read from the receiving clock domain. Due to both sending side and receiving side are operating in different clock domains and a dual-port buffer is used, it can be said as a safe way to transfer multiple bits data between the different clock domains.
A most standard asynchronous FIFO can allow numerous data to be written into it as long as it is not full. The receiving side can also read and obtain numerous data as long as the FIFO is still not empty.
The synchronization of gray code counters is strongly required for the hard work of a FIFO design [11].
2.4.2.2 Passing Numerous Bits CDC Signal Using 1-deep / 2-register FIFO Synchronizer As shown in Figure 2.4.2.2-F1, there is another variation of techniques on transferring the multi-bit data across the different clock domains which consists of a 1-deep two register FIFO.
Figure 2.4.2.2-F1: Block diagram of 1-deep / 2-register FIFO synchronizer [11]
Due to the FIFO is designed by using only one 2-deep dual port RAM, the gray code counters utilized for detection of the empty and full condition are just a basic toggle flip-flop in which the most significant figure of a gray code is similar to the most significant figure of a binary code.
When reset is asserted, both pointers will be reset and the FIFO is not full and empty. This condition of inverted not-full can be used to represent that the FIFO is prepared to accept data.
After a data is inserted into the FIFO, the write pointer will toggle and the FIFO will become full which means when the signal (wrdy) goes low, it will disable the function to toggle the write pointer and thus will also disable the function to insert another data into the 2- register FIFO until the previous data has been read out from the FIFO by the logic of the accepting clock-domain.
This design’s interesting characteristic is that the write pointer is now pointing to the second location in the 2-register FIFO, thus the write pointer will be already to point to the next location to write when the FIFO becomes ready again.
On receiving side of the FIFO, the same concept is replicated and implemented. The FIFO will become not empty when a data is written into the FIFO. The condition of inverted not-empty can be used to represent that the FIFO currently has a data that is prepared to be accepted.
In short, it can use the two registers to store the multiple bits CDC data to reduce one clock cycle from the send Multi-Cycle Path formulation and another cycle from the acknowledge feedback path [11].
2.5 Synchronizing Counters for FIFO Pointer Design