trend powe powe elect contr we w comb in ter custo of th The simu Keyw PAC
the conv circu provi prese so en numb grow lapto Tech supp
* ) For
Low-po
Anbarasu School of 11007, D
Received
Abstrac
An adde d in Nanote er. The Sing er dissipatio tronics devi
rol the moti were used 2
bination of rms of dela om design a he supply-vo
Low-Powe ulated by PS words: SET CS: 73.23.H
1. Intro
The perf performanc volution, co uits is influe
ided to the ented each d
The arith nergy consu
ber and den wing techno
op compute hnology syst
ly leads to p
r corresponde
ower and
u Paulthura f Electronics Dar-Es-Salaa
d 30 July 201
ct
er is an imp echnology i
gle Electron on, high sp ces to repla ion of indiv 24 SET and
input voltag ay, area, po and layout in
oltage scalin er and High SPICE 9.1.
T, Full Adde Hk; 85.35.Gv
oduction
formance of ce of the orrelation an enced by h
designer an day, the pow hmetic circu umption is b nsity of tra ologies in m ers Requires
tems since power consu
ence, E-mail: a
high-per
ai*, Balamur and Telecom m, Tanzania
2; Revised 1
portant elem s moving t n Transistor peed and hi ace conventi vidual electr
d 14 resisto ge. This wo ower, and th n SET proce ng on reduc h-Performan
er, High-Sp v; 85.35.-p.
f many app arithmetic nd digital fi
ow the arit nd used for wer consum uits grows m becoming m ansistors on mobile elec s the use o it is the cor umption red
anbarasu_003
rformance
rugan Dharm mmunication a.
14 Aug. 2012
ment of all towards the r (SET), dis igh perform ional CMO rons in the d ors. The cir ork evaluate heir produc
ess technolo cing the pow
nce 1-Bit S
peed.
plications su circuits to filtering. U thmetic ope synthesizin mption becom
more compl more importa
n a chip an ctronic dev of a Single re element o duction.
@yahoo.com
e 1-bit set
maraj n, St. Joseph
2; Accepted 3
the arithme need of th stinguished mance, is on
S. The SET designed cir rcuit is fun es the perfo ts by hand ogy. Also sh wer expend Set Full-Ad
uch as digita o execute Usually, the erators are ng. As more mes more im lex with the
ant now tha nd faster clo
ices such a e Electron T
of arithmetic
t Full-add
University in
30 Oct. 2012
etic and log he devices,
by a very s ne of the m T technology rcuits. In th
ctioning as rmance of t with logica hown is the ded by leaka
dder digital
al signal pr complex performan implemente e complex a
mportant.
increasing an ever due ock Increas as cellular Transistor F c circuits. D
der
n Tanzania, P
2
gic units. T which cons small device most promis y offers the his Full Add s required f the propose al effort an e considerab
age and sho l circuits h
rocessing de algorithms nce of the i ed in the ce arithmetic ci processor b to the incre sing deman
phones, PD Full Adder Decreasing t
P.O Box
The recent sume low e size low sing nano e ability to der Circuit for all the ed designs
d through ble impact ort-circuit.
have been
epends on such as integrated ell library ircuits are bus width, ease in the d for fast DA’s and r in Nano the power
Anbarasu Pa
106 S controlle size and electron.
of the ele solutions electron 1992 [2]
correspon logic.
2.
S few nano SET cons by tunne transistor effect. Th transmit number o tunnel jun
3.
Q single ele greater th QD. This For QD, in atoms wave fun propertie consider The nano oxide or model ea capacitor depends and C2, current, between (discharg equation
aulthurai, Balam
ingle elect d electron t ultra-low p In 1987, L ectrons is co s have been inverter, m ]. This wor nds to the P
. Basic Ph
ingle Electr ometer usin
sists of a sm el junctions
r, Single ele he electrica the electro of electron nction divid . Quantum
Quantum do ectron can han the the s sensitivity
the discrete and molec nctions betw es of a mol
a metal na oparticle is
organic m ach of the r. The resi
on the size and the ap I depends the electr ging) from
1.
murugan Dharm
ron transis tunneling to ower dissip Likharev has ontrolled by developed made from tw
rk explaine PMOS and N
hysics of SE
ron Transis ng metal, se mall conduc s and capac ectron devic al behaviou on wave, w waves mod ded by the s m Dot [Qd]
ot [QD] is a cause a ch ermal energy y to individu e energy lev cules, so on ween two q lecule. To anoparticle separated molecules so
nanopartic stance is d e of the par pplied volta on V. Whe rodes beca
an initially
maraj / Low-pow
tor (SET) o amplify cu
pation and b s proposed a y a bias appl
on logic cir wo comple ed the prin NMOS tran
ET Operati
stor [SET] h emiconduct cting island
ctively cou ce based on ur of the tun which decrea des that imp
square of wa ]
a mesoscop hange in the
y and can c ual electron vel of the ele
e can talk a quantum do
understand sandwiched from the e o that only
cles-electrod determined
ticle. We d age between
en we start ause movem y neutral na
wer and high-p
is a new urrent. SET based on co a single-ele lied at the c rcuits, mem ementary SE nciples of d nsistors, wh
ion
has been m tor, carbon [Quantum upled to on n an intrinsic
nnel junctio ase expone pinge on the
ave length.
pic system i e electrosta control the ns has led to ectrons in th about “artif ots overlap,
the electro d between t electrodes b tunneling de junction
by the ele denote the r
n the electr t to increas ment of a anoparticle
erformance 1-b
type of s is distingui ontrolling th ectron transi center electr mory and oth
ETs was pr designing c hich can be u
made with c nanotubes Dot] couple ne or more
cally quantu on depends entially with e barrier, w
in which th atic energy electron tr o electronic he QD beco ficial atoms
the couple on transpor two metal e by vacuum
is allowed ns with a
ectron tunn resistors and rodes by V
se V from an electron cost energ
bit set Full-adde
witching d shed by a v he transport
istor in whi rode [1]. Sin
her circuits.
roposed by complemen used to desi
critical dime or individu ed to source
gate. Unli um phenom on how ef h the thickn
hich is give
he addition or Coulom ansport into cs based on
omes pronou and molec d quantum t properties electrodes s or insulatio between th resistor in neling and d capacitors . We will
zero, no c n onto (ch gy by an am
er
device that very small d
of an indiv ich the tunn nce then, va . The first s Tucker et ntary SETs, ign CMOS-
ensions of j ual molecul
e and drain ike Field E menon, the t
ffectively b kness and o en by the ar
or removal mb energy th
o and out o single elec unced, like cules”. Whe dots exhib s in QD. L shown in F on layer su hem. So w parallel w the capaci s by R1, R2
discuss how current can harging) o amount give
uses device vidual neling arious single al. in , that
-style
just a les. A leads Effect tunnel barrier on the
rea of
l of a hat is of the trons.
those en the bit the Let us Fig. 1.
uch as e can with a itance
2, C1 w the flow r off en by
(1)
throu volta
expe Vth, volta remo the a curre Coul
publi cond arbitr comp can b tunne capac junct circu
trans show tunne way throu throu we h
This sup ugh the nan age φ at the
This volt ct a flat zer an electro age, the cu ove) two ele applied volt ent starts to lomb stairca
4. Sing
The pri ications [6, ducting isla
rarily conn ponent of si be consider el junction citance Cj a tion and the uits is the Co 5. Struct
Single-e sfer electron wn in Fig. 1.
el junction for electron ugh the insu ugh the tunn have three t
ppression of noparticles
nanoparticl
tage is calle ro-current r on is added urrent does ectrons onto tage is large o increase ase.
gle Electron
incipals of 7]. Summa ands, tunne nected with ingle electro red as two
and its sch and a resista e thickness oulomb blo
ture of Sin
lectron tran ns form so . A SET is m
consists of ns in one of ulator. Sinc nel junction terminal So
f electron fl only when les such tha
ed threshold regime with d to (remov
not increa o the nanop e enough to again. This
Fig. 1:
n Tunneling
f single-ele arizing, in t l junctions h tunnel ju on tunnelin conductors hematic dia ance Rj, eac of the insu ckade [5].
gle-Electro
nsistors (SE urce to dra made from t two pieces f the metal ce tunneling n flows in m ource, Drain
low is calle the applied at
d voltage an h a width of ved from) ase proporti particles, wh o overcome s leads to
Quantum D
g
ectron elec the single-e s, capacitor unctions, ca ng technolog s separated agram are ch of which ulator. The
on Transist
ETs) are thr ain one by two tunnel j of metal se electrodes g is a discr multiples of n and Gate
d Coulomb d voltage V
nd denoted
f 2 Vth. Wh the nanopa ionally bec hich cost a the Coulom a stepwise
ot Structure.
ctronics ha electron tec rs, and vol apacitors an
gy is the tun by a thin shown in F h depends o
fundamenta
tors
ree-termina one. The s junctions th eparated by to travel to rete process f e, the charg
. As shown
blockade.
V is large en
by Vth. So hen the app articles. Fu ause it req greater amo mb energy o e increase i
ave been p chnology, th
ltage sourc nd voltage nnel junctio
layer of in Fig. 2. It is
n the physic al principle
l switching schematic s hat share a c y a very thin
the other e s, the electr
ge of a sing n in the fig
Current sta enough to e
in the I-V plied voltag urther incre quires us to
ount of ener of two elec in I-V curv
presented he circuits c ces. The is
sources. T on. A tunne nsulating m s characteri cal size of t of SET de
g devices, w structure of common ele n insulator.
electrode is ric charge t gle electron gure, the str
107 art to flow establish a
(2) curve, we ge reaches easing the
o add (or rgy. Once ctrons, the ve, called
in many consist of lands are The basic el junction material. A ized by a the tunnel evices and
which can f SETs is ectrode. A
The only to tunnel that flows [3]. Here ructure of
Anbarasu Pa
108 SETs is a place of p the MOS
6.
In in circui consume switching when bo current fr only a m relatively in SET ci it make u T leakage p does not the therm due to th total pow
B both the supply v construct T addend A outputs th F Full-Add constant inputs (A which co
aulthurai, Balam
almost the pn-junction SFETs [1, 8]
. Low-Pow
n general, th t operation d due to th g occurs, a oth the NSE from the sup minor fracti
y large com ircuits is als up a conside The most sig
power. An change. Ho mal enhance he thermal e wer as the op Because the current lev voltage scal ting low-po The 1- Bit S
A (1-bit pre he sum S, a ig. 3 show der circuit. I and its valu A, B and Ci
orresponds t
murugan Dharm
same as tha ns of the MO
].
F
wer and Hi
here are thre n: dynamic,
he charging and thus, is ET and PS pply to the ion of the mpared to th so a functio erable portio
gnificant co ideal comp owever, in ement of no enhancemen
peration tem dynamic po vel and volt
lability, wh wer SET ci SET Full-ad
ecision), the and the carry s an Intern It consist of ue is 25 mV
in respective to the logic
maraj / Low-pow
at of MOSF OSFETs an
Fig. 2: Schem
igh-Perform
ee compone short-circu g and disch
inevitable SET are tur
ground. Th total dissip he input rise n of operati on of the tot omponent o plementary
a circuit co ormal tunne nt of normal mperature in ower has a tage level r hile device
rcuits.
dder is a ba e augend B y-out Co. nal Circuit o
f 14 PSET a V. The volta ely) of the f
`0', and 25
wer and high-p
FETs. Howe nd a quantum
matic structur
mance 1-Bi
ents that con uit, and lea harging of t
in circuit rned-on sim he power res
pation, as lo e and fall ti
ion tempera tal power.
of the powe circuit doe omposed of eling and c l tunneling ncreases.
quadratic d rise as the
parameters asic arithme B (1-bit pre
of Low-Pow and 14 NSE age sources full-adder a
mV which
erformance 1-b
ever, SETs m dot in pla
re of SET.
it SET Full
nstitute the akage pow the output c
operation.
multaneousl sulting from
ong as the mes. Howe ature, and, a er consume es not dissip f SETs, leak co-tunneling makes up a dependence dimensions s remain co
etic block w ecision), and
wer and Hi T Transisto V1, V2 and and it can correspond
bit set Full-adde
have tunne ace of the c
l-Adder
amount of p er. The dy capacitance Short-circu ly, conduct m the short- output tran ever, the sho as the tempe ed in the SE
pate power kage power g. The static a considerab
on the sup of SETs a onstant, is which has t d the carry- igh-Perform or. The supp V3, shown take only tw ds to the log
er
eling junctio channel regi
power cons ynamic pow e CL when uit power o ting short-c -circuit curr ansient time ort-circuit p erature incre ET circuit r when the r is dissipat
c leakage p ble portion o pply-voltage
are scaled d a key fact three inputs -in (Ci) and mance 1-Bit
ply voltage V in Fig. 2, ar wo values 0 gic `1'. The
ons in ion of
umed wer is
logic occurs circuit rent is es are power
eases, is the
input ed by power of the e, and down, tor in s (the d two t SET Vdd is re the 0.0 V input
109 voltage V1(A) is applied to PSET 1, 4, 7, 10 and NSET of 21, 18, 24, 26 through gate, input voltage V2(B) is applied to PSET 2, 3, 5, 14 and NSET of 17, 19, 20, 22 through gate, and the input voltage V3(Cin) is applied to PSET 6, 8, 13 and NSET of 15, 16, 28 through gate.
The output signals of the full-adder sum is taken from source of PSET 9 and drain of NSET 27, and N6, and the Carry is taken from source of PSET 11 and drain of NSET 25. The presence of positive charge corresponds to logic `1', whereas no charge corresponds to logic
`0'.
Fig. 3: Internal Circuit of Low-Power and High-Performance 1-Bit SET Full-Adder.
Anbarasu Pa
110 7.
T time vari possible output su is logic ‘ logic ‘0’
sum and
8.
T Adder lo scaling is circuit. S 20% of operation are verifi measured Area, an increased adder rea F
Fu applicatio dissipatio
aulthurai, Balam
. Simulati
The logic op iation of th combinatio um and carr 1’ and carry
and carry i carry is log
Fig. 4: S
. Conclusi
The Design ogic circuits s an effecti Simulation r V mDD to n of SET fun fied for the d and tabula nd Delay ar d possibility alizations ca Future Wor
urther this ons. Due t on it can be
murugan Dharm
ion Results
peration of th he input V1
ns of logic ry respectiv y is logic ‘0 is logic ‘1’.
gic ‘0’.
Simulated inp
ion
considerati s have been
ve method results revea maintain o nction base input set a ated. 1 bit S re reduced y for high an be consid rk
s multiplier to the incre used for DS
maraj / Low-pow
he full-adde and V2, re
‘0’ and ‘1’
vely. When 0’. When w When we a
put (A B C) a
ons for Low investigate for the red al that the su overall circu
d adder and and the per SET full ad
than their reduction in dered as a b
r can be ease in spe SP applicati
wer and high-p
er is shown espectively.
to the circu we applied we applied in applied inp
and Simulate
w-Power an ed. It has al duction of p upply-volta uit perform d the circuit
rformance m dder shows
r conventio n power di best choice f
implement eed of mu ions.
erformance 1-b
in Fig. 4. I The piecew uit. The rem
input volta nput voltage
ut voltage [
ed output (SU
nd High-Pe lso been sho power consu age scaling s mance. Truth t is designed metrics of
55% reduct nal adders.
issipation a for the mult
ted in filt ultiplier and
bit set Full-adde
In this first wise consta aining 2 row age [0 0 1] t
e [0 1 1] the [0 0 0] then
UM & CARR
erformance own that the umed by lea should be c h table is a d using PSP
the efficien tion of pow . As techno and area. So
ipliers.
ers for im d high redu
er
3 rows sho ant and app ws are show
then we ge en we get s n we get the
RY).
1-Bit SET he supply-vo akage and s carried out w achieved fo PICE 9.1 Ou nt full adde wer consump
ology scali o 1 bit SET
mage proce uction in p
w the ply all ws the
t sum um is e both
Full- oltage
short- within or the utputs er are
ption.
ing is T full
essing power
111 Acknowledgement
I would like to thank my friends and my faculty members without whom this Journal would have been a distant reality. I also extend my heartfelt thanks to my family and well- wishers.
References
[1] Likharev, K. K, IEEE Trans. Magn. 23 (1987) 1142 [2] Tucker, J. R, J. Appl. Phys. 72 (1992) 4399
[3] Anbarasu Paulthurai, Balamurugan Dharmaraj, International Journal of Computer Applications, 42 (2012) 0975
[4] Mawahib H. Sulieman, Valeriu Beiu, IEEE, 4 (2005) 669 [5] M. M. Abutaleb, Microelectronics Journal, 43 (2012) 537
[6] S. M. Goodnick, J. Bird, IEEE Trans. Nanotechnol. 2 (2003) 368
[7] A. N. Korotkov, R. H. Chen, K. Likharev, J. Appl. Phys. 78 (1995) 2520
[8] U. Hashim, A. Rasmi, S. Sakrani, Int. J. Nanoelectronics and Materials, 1 (2008) 21
