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ii ACKNOWLEDGEMENT

Firstly, I would like to thank my final year project supervisor, Mr. Razaidi Bin Hussin, for his assistance and support throughout the whole project. Without his guidance, I would definitely not be able to finish the project on time. I would also like to thank all of my group members under the same supervision for their help and encouragement. I hope all of us would be able to achieve great success in our future undertakings.

Last but not least, my appreciation goes to my beloved parents. They have been encouraging and supportive all the time. Finally, I would like to thank all my friends and to those who were involved towards completion of this project. Their contributions are really appreciated and without them, this project would not be as it is today. Thanks a lot and may God reward those who had helped me.

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iii APPROVAL AND DECLARATION SHEET

This project report titled Quadrature Decoder with Position and Speed Sensing was prepared and submitted by Noradliyah Binti Mohd Murad (Matrix Number:

071030173) and has been found satisfactory in terms of scope, quality and presentation as partial fulfillment of the requirement for the Bachelor of Engineering (Electronic Engineering) in Universiti Malaysia Perlis (UniMAP).

Checked and Approved by

_______________________

(RAZAIDI BIN HUSSIN) Project Supervisor

School of Microelectronic Engineering Universiti Malaysia Perlis

June 2011

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iv PENYAHKOD KUADRATUR DENGAN PENDERIAAN KEDUDUKAN

DAN KELAJUAN

ABSTRAK

Penyahkod kuadratur digunakan secara langsung dengan pengekod selari atau tokokan untuk mendapatkan maklumat mengenai arah, kedudukan dan kelajuan dari sistem yang berputar. Ia memainkan peranan penting dalam aplikasi kawalan motor.

Projek ini direka untuk mengira kedudukan, kelajuan dan pecutan peranti masukan berdasarkan pada spesifikasi rekabentuk yang diberikan dengan menggunakan Verilog HDL. Rekabentuk ini diselaku dan disahkan menggunakan perisian Altera Modelsim 6.4a. Ragam penyahkodan penuh digunakan untuk peleraian lebih jitu dan ukuran lebih tepat. Pendekatan yang digunakan bertujuan untuk meminimakan penggunaan pendaftar dan menyediakan sistem kawalan yang lebih baik. Pendekatan Verilog HDL yang umum juga digunakan dalam rekabentuk untuk memudahkan penyahpepijatan. Setiap modul memiliki fungsi tersendiri. Penyelakuan dijalankan untuk setiap keadaan masukan bagi memastikan setiap ciri rekabentuk berfungsi. Keseluruhan keputusan membuktikan bahawa rekabentuk yang dijalankan telah berjaya dan memenuhi kehendak spesifikasi rekabentuk.

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v QUADRATURE DECODER WITH POSITION AND SPEED SENSING

ABSTRACT

Quadrature decoder is used for direct interface with linear or incremental encoder to get direction, position and speed information from a rotating system. It plays an important role in motor control applications. This project is designed to calculate an input device position, speed and acceleration based on the design specification given. It is developed using Verilog HDL. The design is simulated and verified using Altera Modelsim 6.4a software. Full decoding mode is used for finer resolution and accurate measurement. The design approaches aimed to minimize the uses of the registers and to provide a better control system. A common architecture of Verilog HDL is built in order to make design easy to debug. Each module designed has its own function. Waveform simulation is done for every possible input condition in order to check the functionality of each design block. The overall result proved that the design is successfully done and has met the design specification.

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vi TABLE OF CONTENTS

Page

ACKNOWLEDGEMENT ii

APPROVAL AND DECLARATION SHEET iii

ABSTRAK iv

ABSTRACT v

TABLE OF CONTENTS vi

LIST OF TABLES ix

LIST OF FIGURES x

LIST OF ABBREVIATIONS xii

CHAPTER 1 INTRODUCTION

1.1 Introduction 1

1.2 Background of Study 1

1.3 Problem Statement 3

1.4 Objectives 4

1.5 Scope of Work 4

1.6 Thesis Structure 6

CHAPTER 2 LITERATURE REVIEW

2.1 Introduction 7

2.2 Overview of Quadrature Encoder 7

2.3 Quadrature Encoders Fundamental 9

2.4 Positioning 10

2.5 Signal Measurement 12

2.6 Velocity and Acceleration Estimation 14

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vii

2.7 Quadrature Encoder Interface Module 15

2.7.1 Enable Digital Filters 16

2.7.2 Increment Pulse Counter 17

2.7.3 Position Counter 17

2.7.4 Reset Pulse Counter 18

2.7.5 Timer Operation 18

2.8 Summary 19

CHAPTER 3 METHODOLOGY

3.1 Introduction 20

3.2 Design Specifications 20

3.3 Digital Filter 23

3.4 Decoding Mode 24

3.5 Quadrature Logic 25

3.6 Implementation of Quadrature Decoder 26

3.7 Index Pulse 27

3.8 Speed and Acceleration Calculation 28

3.9 Analog to Digital Conversion 29

3.10 Register Block 30

3.11 Overall Design Approach 31

3.12 Summary 32

CHAPTER 4 RESULTS AND DISCUSSION

4.1 Introduction 33

4.2 Simulation for Position Detection 34

4.3 Simulation for Time Count 38

4.4 Simulation for Quadrature Decoder 40

4.5 Simulation for Analog to Digital Conversion 42

4.6 Simulation for Register Access 42

4.7 Overall Design Simulation 45

4.8 Reset Test 45

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viii

4.9 Summary 48

CHAPTER 5 CONCLUSION

5.1 Summary 49

5.2 Recommendation 50

5.3 Commercialization 50

REFERENCES 51

TECHNICAL REVIEW PAPER 53

TECHNICAL PAPER 56

APPENDICES

Appendix A 60

Appendix B 63

Appendix C 65

Appendix D 67

Appendix E

69

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ix LIST OF TABLES

Tables No. Page

2.1 Count signal values. 11

3.1 Design specifications for quadrature decoder design. 21

3.2 Lead and lag input signal. 25

3.3 Input addresses for register access. 30

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x LIST OF FIGURES

Figures No. Page

1.1 Signals generated by the quadrature encoder. 2

1.2 Design process. 5

2.1 Typical signals produced by a quadrature encoder [5] 8

2.2 Signals showing forward movement. 10

2.3 Signals showing reverse movement. 10

2.4 Counter state transition diagram [11]. 11

2.5 Edge-to-edge measurement [12]. 13

2.6 Velocity estimation [8]. 14

2.7 QEI module simplified block diagram [5]. 15

2.8 Signal propagation through filter [5]. 16

2.9 Quadrature encoder signals in 4x mode [5]. 17

2.10 Reset by index mode [5]. 18

3.1 Block diagram of the quadrature decoder design. 22

3.2 Block diagram of noise elimination. 23

3.3 Quadrature decoder signals in 4x mode. 24

3.4 Leading and lagging signal position. 24

3.5 Block diagram of decoded signals. 25

3.6 XOR logic for position detection [11]. 26

3.7 Quadrature state transitions [11]. 27

3.8 Flow chart of ADC. 29

3.9 Flow chart of register block. 31

4.1 Waveform for forward direction. 35

4.2 Waveform for reverse direction. 36

4.3 Waveform for forward-reverse direction. 37

4.4 Waveform for time count simulation. 39

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xi

4.5 Waveform for quadrature decoder simulation. 41

4.6 Waveform for analog to digital conversion. 43

4.7 Waveform for registers simulation. 44

4.8 Waveform for overall simulation. 46

4.9 Waveform for reset test simulation. 47

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xii LIST OF ABBREVIATIONS

HDL Hardware Design Language CAD Computer Aided Design

VHDL VHSIC Hardware Description Language VHSIC Very High Speed Integrated Circuit VLSI Very Large Scale Integration FPGA Field Programmable Gate Array CPLD Complex Programmable Gate Array RPM Revolutions per Minute

QEI Quadrature Encoder Interface XOR Exclusive OR

ADC Analog to Digital Converter

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