PPT No Slide Title

Digital Integrated Digital Integrated

Circuits Circuits

A Design Perspective A Design Perspective

Manufacturing Manufacturing

Process Process

Jan M. Rabaey

Anantha Chandrakasan

Borivoje Nikolic

CMOS Process

CMOS Process

A Modern CMOS Process A Modern CMOS Process

p-well n-well

p+

p-epi

SiO₂ AlCu

poly

n+

SiO₂

p+

gate-oxide

Tungsten

TiSi₂

Dual-Well Trench-Isolated CMOS Process Dual-Well Trench-Isolated CMOS Process

Circuit Under Design Circuit Under Design

V_DD V_DD

V_in V_out

M1 M2

M3 M4

V_out2

Its Layout View

Its Layout View

The Manufacturing Process The Manufacturing Process

For a great tour through the IC manufacturing process and its different steps, check

http://www.fullman.com/semiconductors/semiconductors.html

oxidation

optical mask

process step

photoresist coating photoresist

removal (ashing)

spin, rinse, dry acid etch

photoresist stepper exposure

development Typical operations in a single

photolithographic cycle (from [Fullman]).

Photo-Lithographic Process

Photo-Lithographic Process

Patterning of SiO2 Patterning of SiO2

Si-substrate

Si-substrate Si-substrate

(a) Silicon base material

(b) After oxidation and deposition of negative photoresist

Photoresist SiO2

UV-light Patterned optical mask

Exposed resist

SiO2

Si-substrate

Si-substrate

Si-substrate

SiO2

SiO2

(d) After development and etching of resist, chemical or plasma etch of SiO2

(e) After etching

Hardened resist

Hardened resist Chemical or plasma etch

CMOS Process at a Glance CMOS Process at a Glance

Define active areas Etch and fill trenches

Implant well regions

Deposit and pattern polysilicon layer

Implant source and drain

regions and substrate contacts

Create contact and via windows Deposit and pattern metal layers

CMOS Process Walk-Through CMOS Process Walk-Through

p+

p-epi (a) Base material: p+ substrate

with p-epi layer

p+

(c) After plasma etch of insulating trenches using the inverse of the active area mask

p+

p-epi SiO2

SiN3 4

(b) After deposition of gate-oxide and sacrificial nitride (acts as a

buffer layer)

CMOS Process Walk-Through CMOS Process Walk-Through

SiO2

(d) After trench filling, CMP planarization, and removal of

sacrificial nitride

(e) After n-well and VTp adjust implants n

(f) After p-well and VTn adjust implants p

CMOS Process Walk-Through CMOS Process Walk-Through

(g) After polysilicon deposition and etch

poly(silicon)

(h) After n+ source/drain and p+ source/drain implants. These p+

n+

steps also dope the polysilicon.

(i) After deposition of SiO2

insulator and contact hole etch.

SiO2

CMOS Process Walk-Through CMOS Process Walk-Through

(j) After deposition and patterning of first Al layer.

Al

(k) After deposition of SiO2 insulator, etching of via’s, deposition and patterning of second layer of Al.

Al SiO2

Advanced Metallization

Advanced Metallization

Advanced Metallization

Advanced Metallization

Design Rules

Design Rules

3D Perspective 3D Perspective

Polysilicon Aluminum

Design Rules Design Rules

 Interface between designer and process engineer

 Guidelines for constructing process masks

 Unit dimension: Minimum line width

 scalable design rules: lambda parameter

 absolute dimensions (micron rules)

CMOS Process Layers CMOS Process Layers

Layer

Polysilicon Metal1 Metal2

Contact To Poly

Contact To Diffusion Via

Well (p,n)

Active Area (n+,p+)

Color Representation

Yellow Green

Red Blue

Magenta Black Black Black

Select (p+,n+) Green

Layers in 0.25

Layers in 0.25   m CMOS process m CMOS process

Intra-Layer Design Rules Intra-Layer Design Rules

Metal2 4

3 10

0 9 Well

Active 3

3

Polysilicon

2

2 Different Potential

Same Potential

Metal1 3

3 2

Contact or Via

Select

2 or6

Hole 2

Transistor Layout Transistor Layout

1

2

5 3

Transistor

Vias and Contacts Vias and Contacts

1

2

1 Via

Metal to Poly Contact Metal to

Active Contact

1

2

5 4

3 2

2

Select Layer Select Layer

1

3 3

2

2

2

Substrate Well

Select 3

5

CMOS Inverter Layout CMOS Inverter Layout

A A’

p-substrate n Field

Oxide p⁺

n⁺ In

Out

GND V_{D D}

(a) Layout

A A’

Layout Editor

Layout Editor

Design Rule Checker Design Rule Checker

poly_not_fet to all_diff minimum spacing = 0.14 um.

Sticks Diagram Sticks Diagram

1

3

In Out

V DD

GND

• Dimensionless layout entities

• Only topology is important

• Final layout generated by

“compaction” program

Packaging

Packaging

Packaging Requirements Packaging Requirements

 Electrical: Low parasitics

 Mechanical: Reliable and robust

 Thermal: Efficient heat removal

 Economical: Cheap

Bonding Techniques Bonding Techniques

Lead Frame Substrate

Die

Pad

Wire Bonding

Tape-Automated Bonding (TAB) Tape-Automated Bonding (TAB)

(a) Polymer Tape with imprinted

(b) Die attachment using solder bumps.

wiring pattern.

Substrate Die

Solder Bump Film + Pattern

Sprocket hole

Polymer film Lead frame Test

pads

Flip-Chip Bonding Flip-Chip Bonding

Solder bumps

Substrate Die

Interconnect layers

Package-to-Board Interconnect Package-to-Board Interconnect

(a) Through-Hole Mounting (b) Surface Mount

Package Types

Package Types

Package Parameters

Package Parameters

Multi-Chip Modules

Multi-Chip Modules