Dr. Waleed Alasmary
Sequential Circuits
Sequential Circuits
Combinational circuits
Output = f (present inputs)
Sequential circuits
Output = f (present inputs &
past inputs)
Circuit remembers past history
Must contain memory
Sequential Circuits (cont’d)
A sequential circuit is specified by a time sequence of inputs, outputs, and internal states (what about the combinational circuits?)
Two main types of sequential circuits according to the timing of their signals:
A synchronous sequential circuit
It is a system whose behavior can be defined from the knowledge of its signals at discrete instants of time
An asynchronous sequential circuit
It is a system whose behavior depends upon the input signals at any instant of time and the order in which the inputs change
Synchronous Sequential Circuits
A synchronizing, periodic signal, Clock, facilitates the transition from
present state to next state
The storage elements (memory) used in
clocked sequential circuits (synchronous sequential circuits) are called flip-flops
A flip-flop is a binary storage device capable of storing one bit of
information
Latches vs. flip-flops
Latches
Storage elements that operate with signal levels (rather than signal transitions) are referred to as latches
Latches are said to be level sensitive devices
Latches are useful for the design of asynchronous sequential circuits
They are not practical for use as storage elements in synchronous sequential circuits
They are the building blocks of flip-flops
Flip-flops
Storage elements that control by a clock transition are flip-flops
Flip-flops are edge-sensitive devices
SR (Set Reset) Latches with NOR gates
SR = 11 is avoided
Outputs are not complementary
Input transition from 11 00 may cause circuit to enter an unpredictable or undefined state or a metastable state
SR (Set Reset) Latches with NAND gates
SR = 00 is avoided
Outputs are not complementary
Input transition from 00 11 may cause circuit to enter an unpredictable or undefined state or a metastable state
SR (Set Reset) Latches with control Input
C = 0
Latch retains its state
C = 1
Allows propagation of SR inputs
Data (D) Latch
One way to eliminate the undesirable condition of the
indeterminate state in the SR latch is to ensure that inputs S and R are never equal to 1 at the same time
Flip-Flops vs. Latches
Controlled latches are level-triggered
Flip-Flops are edge-triggered C
CLK Positive Edge
CLK Negative Edge
Edge-Triggered D Flip-Flop
A change in the output of the flip-flop can be triggered only by and during the transition of the clock from 1 to 0
Master–slave D flip-flop
The output may change only once
A change in the output is triggered by the negative edge of the clock
The change may occur only during the clock’s negative level
Edge-Triggered D Flip-Flop (cont’d)
Another construction of an edge-triggered D
flip-flop uses three SR latches as shown in Fig.
5.10
Two latches respond to the external D (data) and Clk (clock) inputs.
The third latch provides the outputs for the flip- flop
Edge-Triggered D Flip-Flop (cont’d)
It is similar to the symbol used for the D latch, except for the arrowhead-like symbol in front of the letter Clk,
designating a dynamic input
The dynamic indicator (>) denotes the fact that the flip- flop responds to the edge transition of the clock
Edge-Triggered D Flip-Flop (cont’d)
Other Flip-Flops
The most economical and efficient flip-flop constructed in this manner is the edge-triggered D flip-flop, because it requires the smallest number of gates
Other types of flip-flops can be constructed by using the D flip-flop and external logic gates
Three operations that can be performed with a flip-flop
Set it to 1
Reset it to 0
Complement its output
JK Flip-flop
Versatile flip-flop
It can be Set
It can be reset
It can complement (toggle) its output
T (toggle) flip-flop
The T (toggle) flip-flop is a complementing flip-flop can be obtained from JK flip-flops or can be constructed using D flip-flops
Flip-Flop Characteristic Tables
D Q Q
D Q(t+1)
0 0
1 1
Reset Set
J K Q(t+1) 0 0 Q(t)
0 1 0
1 0 1
1 1 Q' (t)
No change Reset
Set Toggle J Q
Q K
T Q Q
T Q(t+1) 0 Q(t) 1 Q' (t)
No change Toggle
Flip-Flop Characteristic Equations
D Q Q
D Q(t+1)
0 0
1 1
J K Q(t+1) 0 0 Q(t)
0 1 0
1 0 1
1 1 Q' (t) J Q
Q K
T Q Q
T Q(t+1) 0 Q(t) 1 Q' (t)
Flip-Flop Characteristic Equations
Analysis / Derivation
J Q
Q K
J K Q (t) Q (t+1)
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0
No change Reset
Set Toggle
Analysis of Clocked Sequential Circuits
D Q Q
CLK
D Q Q
A
B
y x
State Table (Transition Table)
D Q Q
CLK
D Q Q
A
B
y x
A(t+1) = A x + B x B(t+1) = A’ x
y(t) = (A + B) x’
Present
State Input Next
State Output
A B x A B y
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
t+1 t
t
0 0 0 0 1 0 0 0 1 1 1 0 0 0 1 1 0 0 0 0 1 1 0 0
State Table (Transition Table)
D Q Q
CLK
D Q Q
A
B
y x
A(t+1) = A x + B x B(t+1) = A’ x
y(t) = (A + B) x’
Present State
Next State Output x = 0 x = 1 x = 0 x = 1
A B A B A B y y
0 0 0 0 0 1 0 0
0 1 0 0 1 1 1 0
1 0 0 0 1 0 1 0
1 1 0 0 1 0 1 0
t+1 t
t
State Diagram
D Q Q
CLK
D Q Q
A
B
y x
0 0 1 0
0 1 1 1
0/0
0/1
1/0
1/0
1/0
1/0 0/1
0/1
AB input/output
Present State
Next State Output x = 0 x = 1 x = 0 x = 1
A B A B A B y y 0 0 0 0 0 1 0 0 0 1 0 0 1 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 0 1 0
Analysis with JK Flip-flop
Procedure
Determine state
equations (transition equations)
Determine the state table (transition
table)
Determine state diagram
