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DESIGN AND ANALYSIS OF THREE STAGE VOLTAGE CONTROLLED OSCILLATORNamrata Patkar1, Rishi Choubey2
1Research Scholar, Dept. of Electronics and Communication Engineering, SVN University, Sagar (M.P)
2Assistant Professor, Dept. of Electronics and Communication Engineering, SVN University, Sagar (M.P)
Abstract- This work will present a more accurate frequency prediction model for single-ended ring oscillators (ROs), a case-study comparing different ROs, and a design method for LC voltage-controlled oscillators (LCVCOs) that uses a MATLAB script based on analytical equations to output a graphical design space showing performance characteristics as a function of design parameters. There are advantages in average power dissipation and area for a minimal trade off in tuning range with the varactor-tuned ring oscillator. Four multi-GHz LCVCOs were designed in the Global Foundries 28 nm HPP CMOS technology: 15 GHz varactor- tuned NMOS-only, 9 GHz varactor- tuned self-biased CMOS, 14.2 GHz digitally-tuned NMOS- only, and 8.2 GHz digitally-tuned self-biased CMOS. As a design method, analytical ex- pressions describing tuning range, tank amplitude constraint, and start up condition were used in MATLAB to output a graphical view of the design space for both NMOS-only and CMOS LCVCOs, with maximum varactor capacitance on the y-axis and NMOS transistor width on the x-axis. Phase noise was predicted as well. In addition to the standard varactor control voltage tuning method, digitally- tuned implementations of both NMOS and CMOS LCVCOs are presented.
1 INTRODUCTION
The rapid growth in global communications networks has driven the demand for high-performance communications systems that are faster and consume less power. In fiber optic channels, the interface circuits at the emitting and receiving ends need to be fast enough to take full advantage of the speed of the fiber optic system.
Within-high performance mobile devices, microprocessors require a phase-locked loop (PLL) for frequency synthesis to generate a stable clock, clock and data recovery (CDR) for high speed IO’s, and wireless transceiver front-end circuitry that must be capable of modulating high-speed analog signals incoming from the antenna. Voltage- controlled oscillators (VCOs) are used within PLLs for these applications, and in modern devices, must achieve center frequencies in the GHz range [1–8].
In such applications, the VCO must have low phase noise first and fore- most, low power consumption, and must be implemented within a reason- able area. CMOS VCOs are typically designed using a ring oscillator (RO) or an LC resonant voltage-controlled oscillator (LCVCO). LC oscillators
generally have better phase noise performance due to the high quality factor (Q) achievable with an LC resonant network; however, high-Q designs require high quality on-chip inductors, increasing the cost and complexity of the CMOS process. Even though the concept of the VCO is fairly straightforward, there are still difficulties in the design, especially in advanced scaled deep sub-micron CMOS technologies. The continued scaling of CMOS technologies wors- ens short-channel effects, increases process variation and device mismatch, increases the influence from parasitic components, and increases flicker and thermal noise [9].
The design of VCOs includes trade-offs in speed, power, area, and ap- plication. Accurate models and analytical expressions are needed in or- der to shorten and simplify the design process. Without accurate models, the designer will not be able to make informed decisions on which design variables affect important performance parameters and may have to rely on iterative and time- consuming simulations. This is not a recommended
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design approach. Furthermore,assembling analytical expressions together into a numerical computing environment such as MATLAB and generating a graphical view of the design space can give the designer a powerful insight, making the initial design as time-efficient as possible.
1.1 VCO
The voltage-controlled oscillator (VCO) is a circuit where the output is a single-ended or differential periodic oscillating output voltage the frequency of which is dependent on an input control voltage. A basic VCO symbol is shown in Figure 1.
Figure 1: Basic VCO symbol.
Figure 2: Simple 2-port feedback circuit with amplifier and feedback
network
The VCO is a critical circuit block used in phase-locked loops (PLLs). Common applications of PLLs are in frequency synthesis and clock and data recovery circuits (CDR) where they are used as a local VCO. The two main categories of VCOs include the ring oscillator and the LC oscillator (LCVCO). The LCVCO is generally capable of higher maximum oscillation frequencies as well as better phase noise performance compared to ring oscillators. Ring oscillators are advantageous in tuning range and manufacturability.
The PLL is a circuit that synchronizes
the frequency and phase of its output signal to the frequency and phase of a reference input signal [11]. The phase detector produces a DC output Ve that is proportional to the phase difference of the input signal Xi and the VCO output signal Xo. The low- pass filter attenuates any high frequency variation in Ve, giving a clean DC signal, Vc, to the VCO. This signal controls the frequency of oscillation of the VCO, decreasing or increasing until the frequency of Xo matches that of Xi. When the difference in angular frequency of the input and output (ωi−ωo) is much lower than the loop gain (K = KdKv), the PLL is in lock.
One common application for PLL is the clock and data recovery circuit (CDR) shown in Figure.
Figure 3: Block diagram of CDR 2 PROPOSED RING VCO
Addition of an extra nMOS transistor based ring VCO is proposed in this paper. The variable resistance is implemented using nMOS transistor and added at the input terminal of each inverter as shown in Fig.
The oscillation frequency of ring VCO depends on transconductance (Gm), variable resistance (RV) and capacitance (CG). However, Gm and CG are device parameters and assumed to be constant. The approach of wide frequency range of the voltage-controlled ring oscillator is achieved by controlling the resistance [9].
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Figure 4 Proposed three stages RingVCO
3 SIMULATION RESULTS FOR PROPOSED THREE STAGE RING VCO The output waveform of proposed three stages ring VCO is shown in Fig.
Figure 5 Output waveform of proposed three stage ring VCO Table I shows the output frequency of proposed three stage ring VCO which increases with the increase in applied control voltage. Control voltage has been varied from 1V to 3.0 with corresponding output frequency from 2260.65MHz to 3441.71 MHz with variation in power consumption from
31.08μW to 52.21μW.
Table I Simulation Results for Proposed Three Stage Ring VCO
The proposed ring VCO shows higher frequency range as compared to existing current starved ringVCO .
Figure 6 Variations of frequency with control voltage
Figure 7 Variations of Power consuption with control voltage 4 CONCOLSION
Improved performance ring VCO has been presented in this paper. The output frequency shows almost linear relationship with the control voltage.
The performance of proposed three stage ring VCO has been compared with existing one and shows better performance in terms of power consumption and frequency range as compared to existing current starved ring VCO.
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