Aspects of designing a high speed analog to digital converter

tss.ll

Aspects of Designing a High SPeed Analog To Digital Converter

M.S. Hsu postgraduate student

Thesis submitted for the degree of Master of Engineering

^Science

The University of Adelaide

(Department of Electrical ancl Electronic Engineering) 10 September 1992

ln

I I

l

l

,iI

I

I I

tI

I

{

Contents

1 Introduction

1.1

An introduction

to

Analog to Digital Converter

1.2

^ADC architectur-es in silicon

I.2.7

^{Flash converter}

1.2.2

Pipeline Converter

1.2.3

Subranging ADC

L2.4

Successive Approximation ^Converter

L2.5

^{Dual Slope Converter}

1.2.6

Summary of ADC architecture ^.

Efforts ^towarcl high speed and high ^accuracy

ADC '

^'

The scope of this thesis 1.3

1.4

2 The review of the scaling

effects

on silicon MOS

2.L

Scaling Models

2.I.7

^{Scaling Factols}

2.1..2

^Summaly

2.2

Observations and Limitations of Scaling

1

1

4

4

5

ta I

8

10

11

11

16

19 20

2t

24

26

2.2.2

Limits of Miniatulisation ^.

2.2.3

^{Limits of} Interconnect and Contact ^Resistance

2.2.4

Lirnits of Subthreshold Current

2.2.5

^{Limits of} Logic Level and Supply Voltage by Noise

2.2.6

Lirnits of Current ^DensitY

2.3

^Conclusion

3 An ADC

^design

using GaAs technology

32

35

4t

42 49

51

52

53

Ðt

59

62

bt

69

lô

II

81 3.1

3.2

ooù.Ð

3.4

Intloduction to GaAs clevices

3.1.1

Advantages of GaAs over silicon

3.1.2

Technologies of GaAs

3.1.3

Comparison of GaAs device pelformance

3.1.4

^The fabr-ica,tion process of MtrSFtrTs

3.1.5

^The disadvanta'ges of GaAs over silicon

3.1.6

^The Hysteresis ancl Olfset of GaAs MESFETs The ADC architecture

3.2.I

^The configulations of the ADC

3.2.2

The lefelence sampling comparator

3.2.3

The offset cancellation ^scheme The realisation of the ADC in GaAs

3.3.1

Technology used

3.3.2

^The gener-ation of 256 reference voltages

3.3.3

^{The clesign of a'n analog switch}

The realisation of the comparator

52

55

64

7I

77

83

ll

87

3.4.1

A bootstrapping structure for hysteresis reduction

4 ADC perforrnance optirnisation

4.1

^{The effect of} offset cancellation on pelformance

4.2

The compar-atol gain and operating range

4.2.7

The equivalent circuit and the analysis for gain

4.2.2

The factors affecting voltage ^gain

4.2.3

Summat'y of gain constraints

4.3

The factors affecting operating ^speecl

4.4

Compalatol palarrretels

5 The layout of the ADC

5.1

^{Layout tools}

5.2

^{General layout} consiclelations

5.3

^{Thermal clesign}

Some layout techniques

5.4.1

Contlol of absolute value

5.4.2

^The layout of vely ^la,rge transistols

5.4.3

Matchingstluctule

5.4.4

lVlatching thelmal effects

5.4.5

Matching shape ancl size

5.4.6

^{Minimurn distance for matchecl clevices}

5.4.7

^Matching common-centloid ^geometries

5.4.8

^Matching orientation

92

99

5.4

98

..105

106

108

.

126

\27 t46 L49

150

r52

155

tôl

.

t57

159

i60

160

..161

161

161

,

¹⁶²

5.4.9

Matching the surlottnclings

...162

5.4.10 Compensation for interconnect

5.5

^The layout of the ADC

5.5.1

^{The floor plan}

5.5.2

^The compalator modules ^.

5.5.3

^Layout of the switch

5.5.4

^{Layout of the resistor ladder}

5.6

Comparator layout

5.7

^{The layout of a}

bit

^{slice ancl a test chip}

6

Discussion

and future work

6.1

^{The error sources in the design}

6.1.1

Hysteresis and offset voltage

6.2

^{Futrre work}

6.2.I

^Error correction algorithm

6.3

The elirnination of ^self calibration

6.3.1

^{The use of a depletion mode MESFET}

6.4

^Conclusion

A Analysis of the self calibration time

B Low frequency analysis of the

source

follower

8.1

Differential ampiifiel low frequency analysis

C High frequency analysis of the comparator

165 164

165 166

168

.

¹⁷⁰

178

,

r82

185 185

.

¹⁸⁷

190

191

792 193

.

¹⁹⁶

198

202

244

1V

208

This ^rvork conlains no material ^rçhich has been accepled for the a*'ard ^of an-r'olher degree or diploma in any'uni\,'ersill'or otìrer

terliary'instilution

^{and to the besl} of rny'knorvledge and belief, contains no malerial previousl."- published or

*'ritten

^b1' another person) except rvhere due reference has been made

in

the

text'

I

give consent

to

this

cop!'of

m,v thesis, $'hen deposiled in the university Library, ^being available for loan and photocopf ing

Jon2ç , t77)

SIGN ED

DATE

I

I

Acknowledgements

I

would like

to

express my gratitute

to

the people who made

their

contributions

to

the completion of this research. First of all

I

would like

to

thank my supervisor, ^Associate Professor

Dr. K.

Eshraghian

for

his guidance and overall support during

my

stay in

this University.

^Andrew Beaumont-Smith is

the

second person

I

would

like to

thank' Without his help in faciiitating the CAD ^{system, the} tutorials for ^using the ^{software and} correcting my english,finishing this thesis would ^{have been} much much

later'

My partner

Dr.

Bertrand Hochet of EPFL Switzerland has given me special assistance in this research during his six months stay here. Derek Abbott helped me to organise the structure ^of this thesis. Finally, the friendship and assistance which

I

have received from the colleagues and staff of the d.epartment have made my ^stay in the University much more enjoyable. I would like to thank them ^all.

VI

Abstract

Analog

to

Digital Convelte-,.s operating in the microwave frequency are neecled in digital telecommunications, optical data transmission systems and real

time

signal processors.

The fastest ADC repolted using BìCMOS technology can operate

at

650M samples per second ancl offers 8-bit resolution. The high power dissipation is the ma,in drawback of using bipolar silicon technology. The progress of scaling silicon devices is limited by both the clevelopment of process technology and the fabrication equipment. Thus,, a low po\ryer' high speed ADC using silicon technology is not ^possible at the present

time.

^On the other hand, Gallium Alsenide technology is vely promising for high frequency operation with lower po\Mer consumption.

A

Gallium Arsenide ADC opelating

aI

2.2 GHz ^{has been} re-

ported, howerreL

it

^{only ofiers 5-ltit} resolution, which limits its use

to

a srnall number of applications. Designing a high speed and high accuracy ADC using GaAs involves many complex issues, the two

majol

obstacles

limiting

the accuracy are offset and hysteresis.

Therefore, the main objective in this resealch plogram is to ^aclch'ess these important issues.

Among many existing techniques

of ADC

design, a subranging architectule is selected

primarilv for its simplicity ^{and high speed} potential. The problem of a long sampling time

neeclecl

in

a conventional "input ^voltage sampling" ^scheme is eliminated by the use of a

"refelence voltage sampling" approach. MoLeover, a very simple feeclback structure and

input coupling capacitols ale acla,ptecl to perform an offset-flee conversion. In overcoming the hysteresis proìrlems a "bootstrapping" ^{technique is used} to clamp the dlain-to-source voltage of the transistols which are subject to hystelesis. This is normally perfolmed by cascoding scherres fol hysteresis recluction. An ADC ^aimed at 8-bit and 1 GHz with a 1V

compromise is achievecl by the ^choice of device parametels. The simulation ^{results show}

that

the clesign can reach S-bit resolution

at

a

late of

700M sarnples

pel

second, with 256mW power dissipation for the analog

circuit. In

addition, the ^use of small transistor sizes makes the entir-e ADC lealisable on a 3mm by 3mm chip.

v111