Before going into details of the design, basic principles of the digital-to-analog converter (DAC), delta-sigma modulator (DSM), LC voltage-controlled oscillator (VCO) are discussed in Chapters 2, 3 and 4 respectively. The startup of The oscillators are also explained using two approaches, the Barkhausen criterion and the negative resistance theory. The frequency resolutions of the proportional and integral paths are different, but the structures are identical.
Impulse response of the LC VCOs (a) when the pulse is on peak (b) when the pulse is on.
INTRODUCTION
MOTIVATION AND RESEARCH OBJECTIVES
This thesis focuses mostly on DCOs that have high frequency resolution while providing low phase noise and its components, i.e., DSM DAC and LC VCO. Chapter 5 explores the analysis and design of DCOs and describes an implementation of DCOs along with experimental results and design considerations. Due to non-ideality, such as noise, the effective resolution of N-bits DAC can be less than N-bits.
The analog output always follows the sign of the digital input changes, the DAC is supposed to be monotonic.
RESISTOR DACS
- STRING RESISTOR LADDERS
- R-2R RESISTOR LADDERS
Therefore, it is recommended to insert an OP-AMP at the output of the DAC to buffer the output impedance to ensure a low impedance for the next block. The main disadvantage of series resistor ladders is that they require a huge number of resistors and switches for fine resolution. As the bits are set to 0 or 1, the output voltage will take a corresponding value between VLOW and VHIGH - the minimum step.
V OUT = V HIGH × D_IN 2 n
CURRENT-STEERING DACS
Among the variety of DACs, the current steering topology has the highest operating frequency and then becomes a reliable solution for GHz applications[4]. When a switch turns off, the top node discharges from its corresponding current source to zero. Moreover, the ground voltage fluctuates a lot because the switching actions dynamically change the total current.
The problems of current switching topology can be successfully suppressed by using current control topology (Figure 5). Thanks to the differential pair, the tail current is steered to the left or right, causing tiny voltage fluctuations at the upper node of the current source. Another fault is that the digital input signal is not the rail-to-rail regime to ensure that all the differential pair also work at the saturation cause, which requires additional pulse generator.
- RANDOMIZATION
- BASIC NOISE SHAPING
At the expense of eliminating the fractional tailings with modulus randomization, the high phase noise is increased. Such high-level quantization noise is created by approximating a fractional value using only two coarse values, 0 and 1, so that the resolution is limited to 1. Today, modern applications solve this problem by transforming the phase noise to the high-pass form. By using the high-pass shaping technique, the quantization noise can be remarkably reduced, as long as an additional low-pass filter is applied.
High-pass shaped phase noise and low-pass filter transfer function to be convoluted (b) and the residual phase noise (c) after applying low-pass filter to the high-pass shaped phase noise. Generating sequence b(t) to make a high pass shaped noise is called "noise shaping". We now consider noise generation in z-domain with negative feedback system shown below in Figure 7. This comparison implies that high order DSM shapes noise more sharply compared to 1st order DSM.
2 nd order noise shaping 16
1 st order noise shaping
LC VOLTAGE-CONTROLLED OSCILLATOR (VCO) FUNDAMENTALS
- BASIC OSCILLATOR CHARACTERISTICS
- LC RESONATORS
Today, many communications applications prefer to use LC VCOs due to their low power, low jitter and broadband performance. For example, if we also consider the frequency response range (FTR) of the VCOs, FOMT is defined as follows. In the ideal tank (a) there are no lossy components, but in practical design we should consider the tank as lossy tank (b).
In the ideal case, at the resonant frequency, the tank impedance goes to infinity, but in the ideal case, only Rp.
Z TANK (j2πf)|
Ideally, at the resonant frequency the impedance of the tank goes to infinity, but ideally only Rp. 14) Quality factor (Q-factor) is one of the important parameters in LC VCO. Since the LC tank is an inherent bandpass filter, a sharper response means improved filtering capability. Therefore, a high Q-factor LC VCO has better phase noise performance because noises other than the resonant frequency are more filtered.
INTERGRATED INDUCTORS
Thus, when dealing with ultra-high frequency LC VCOs such as mmW band, avoiding such phenomena is crucial. Stacking more metals, fewer turns, or a wide-bandwidth inductor can be considered to push the self-resonant frequency.
INTEGRATED CAPACITORS
Despite its high manufacturing cost, it is widely chosen for its linearity, durability and high capacity density.
Plus
Minus
CTM CBM
START-UP OF LC VCOS
This implies that if the loop gain is unity and phase shift is integer multiples of 2π, the feedback system can oscillate. Since inductor and capacitor are not seen (equivalent impedance becomes infinite) at the oscillator frequency, excluded. This inequality implies that to ensure safe starting of LC VCOs, Q factor of tank and transconductance of gm cell must be large.
This approach can also have the same result as the Barkhausen criterion. a) Ideal LC tank and (b) Lossy LC tank with negative resistance. As shown in Figure 16 (b), Rp and -Rp cancel each other out so that only the ideal inductor and capacitor remain that can sustain oscillations similar to (a). In both cases suggest for stable oscillation, gm and Rp should be large enough.
LC VCO TOPOLIGIES
Because of the inherent characteristics of the tank filter, harmonics are rejected and only the fundamental tone is injected into the tank.
As shown in the current waveform, the current-controlled left PMOS and right NMOS, right PMOS and left NMOS transistors turn on and off in a staggered manner, and their conduction angle is π. It is possible to decompose the current waveform in a conventional and differential manner, as the NMOS type did. As shown in Figure 21, there is no common current, only differential current.
In the same way as the NMOS type, the differential mode current waveform can be expressed using Fourier series.
6dB NMOS-type
CMOS-typePN
LEESON’S PHASE NOISE MODEL
That is, the VCOs are LTI system and the noise comes only from the LC tank. But with these assumptions, it is sufficient that the equation follows the general trend and understands phase noise. Later Leeson modified the phase noise model to include a flicker noise dominant region and flat region.
This equation assumes that the corner 1/f3 and the corner 1/f2 occur exactly at the corner 1/f, but in real cases this is not the case. Although this equation is very simple and intuitive, it is difficult to know the effect of other parameters that are not included in this equation.
IMPULSE-SENSITIVE FUNCTION (ISF) MODEL
Which means, VCOs are vulnerable to noise when the magnitude of the ISF is large.
DESIGN OF 12−14.5 GHZ DIGITALLY-CONTROLLED OSCILLATOR (DCO) FOR ULTRA-LOW-JITTER PLL
- OBJECTIVE AND MOTIVATIONS
- DESIGN OF DELTA-SIGMA DAC
DLF+DSM
TUNE
DESIGN OF LC VCO
Designing high-performance LC VCOs is essential since the performance of the oscillator determines the overall performance of the PLL. Since the target frequency is high, the gm cell of the VCO should be thin transistor to reduce the parasitic capacitance. Also, the CMOS-type topology is chosen because, in thin-transistor NMOS-type LC VCOs, the gate oxide is easily broken.
For superior phase noise performance, the hvt device is used for the gm cell to prevent the transistors from operating in the deep triode region. The inductance value is related to the oscillation frequency, frequency tuning range, phase noise performance and power consumption. In this design the 200 pH inductor is used and its shape is calculated to have the maximum Q factor.
Typically, the full frequency of the inherent high-pass filter is 20 times the oscillation frequency. As the W/L ratio of the transistor increases, the Q-factor of CBANK increases as Ron decreases. Since CBANK is binary weighted, R becomes half and the transistor size doubles as the bit increases.
Once the CBANK design is completed, determine the dimensions of the varactor to meet the given KVCO specification. Varactors are thick devices because the leakage current of thin devices is significant, which causes reference traces in PLL.
VBIAS VTUNE
For the main circuit, to make 50 MHz/V of KVCO, the varactor capacitance is 22-28 fF. Similarly, for the auxiliary circuit, to make 50 MHz/V of KVCO, the varactor capacitance is 124-192 fF. The size of the gm cell is directly related to the overall frequency, onset, noise and power of the VCO.
Typically, we set the startup margin about three times larger than the Barkhausen criterion to ensure the oscillation of VCO under PVT variations. After the start-up margin has been met by changing the W/L ration, the next step is to change the size of the cell. Even when the layout is done, we have to go back to the schematic level unless the specifications are met.
M 1 M 2VDD
SIMULATION AND EXPERIMENTAL RESULTS Delta-sigma DAC
As the DAC input code is reduced, the output of the low-pass filter is also reduced. Thanks to DSM, the resolution of the DAC is significantly increased, and the low-pass filter eliminated high-frequency components. The solid line is the schematic simulation result and the dashed line is the PEX simulation result.
Due to the parasitic capacitance, the PEX RP simulation is reduced from 115 Ohm to 97 Ohm compared to that of the schematic simulation. Therefore, in the scheme, the starting margin is about 3, but in PEX, the starting margin is almost less than 3. In the scheme, the frequency tuning range is 14-18.5 GHz, which is higher than the target frequency to accommodate the frequency reduction caused by the parasitic capacitance in layout.
As shown in the graph, both main loop and auxiliary loop KVCO meet the target specification, 52MHz/V and 550MHz/V for each. Simulation results of KVCO for (up) main loop (down) auxiliary loop when VTUNE is changed from 0.2 to 1.0V. The flicker noise corner is less than 500 kHz, which does not degrade the jitter performance of the PLL.
This is the effect of parasitic induction and dummy metal that PEX does not count. The FOM of the VCO at a frequency offset of 1 MHz is less than 184 dB when the phase noise is -109 dBc/Hz and the power consumption is 5.5 mW.
CONCLUSIONS
ACKNOWLEDGEMENTS
