Stefan Nikkei Microdevices Memory Symposium 012605

(1)

Intel

’

s Memory

Strategy for the

Wireless Phone

Stefan Lai

VP and Co

-

Director, CTM

Intel Corporation

Nikkei

Microdevices

Memory Symposium

January 26

(2)

Agenda

y

Evolution of Memory Requirements

y

Evolution of the Memory Subsystem

y

Evolving Role of Storage

y

(3)

y

Evolution of the Memory Subsystem

y

(4)

WW Adoption of New Handset Features

Mainstream Adoption Differs Worldwide

--

Handset needs diverge as segmentation increases

--

Features driving RAM, code & data density increase

--

Data needs highly variable, driving growth of card sockets

0% 25% 50% 75% 100%

Packet Data: +18 Mb

Packet Data: +18 Mb

Color: +46 Mb

Camera: +202 Mb

3G: +402 Mb

2000 2001 2002 2003 2004 2005

Source: NPD/

(5)

Today

’

s Memory Subsystem Needs

y

ySRAMSRAM

y

yPSRAM PSRAM

y

yLPS/DDR DRAMLPS/DDR DRAM

y

y<100 ns bit alterations<100 ns bit alterations

y

y<500 <500 µµA retention powerA retention power

y

y_≥_≥101088write cycleswrite cycles

y

ySmall Form Factor HDDSmall Form Factor HDD

y

yNANDNAND

y

yMLC NORMLC NOR

y

yLow costLow cost

y

y0.5 to 2 MB/s write0.5 to 2 MB/s write

y

y≥_≥101055erase cycleserase cycles

Technologies

’

05 Requirements

Memory Function

Working

User

Static

System

Execution

RAM

Code

Data

y

yMLC NORMLC NOR

y

ySBC NORSBC NOR

y

yLPS/DDR DRAM + LPS/DDR DRAM +

storage

storage

y

y_≤_≤104 MHz random read104 MHz random read

y

yVery low retention powerVery low retention power

y

(6)

Needs Vary Greatly by Handset Segments

Hardware BO

M

Low

312 mu handsets

High

68 mu handsets

Mid

281 mu handsets

Functionality

Execution Memory

Execution Memory

16 to 64 Mb

System & User Data

2 to 32 Mb

Working Memory

64 to 128 Mb

64 to 256 Mb

64 to 128 Mb

Working Memory

128 to 512 Mb

Execution Memory

256 to 512 Mb

256 to 512+ Mb

High End

(7)

y

(8)

Memory Hierarchy & Trends:

Evolution of the Subsystem

y

Integrated memory for Cache &

Buffers on the rise

–

Emergence of 2nd Level Cache

in Wireless CPUs

y

Large integrated memory appears

in mainstream chipsets

–

Size of embedded volatile

memory remains limiting factor

y

System in Package use growing

–

New technologies enable size,

power, & performance gains

–

Flexibility & scalability are key

Increasing Latency,

Decreasing Cost/Bit

Increasing Latency,

Decreasing Cost/Bit

BB/App

CPU BuffersBuffers

2

2ndnd_{Level Cache}_{Level Cache}

1

1stst_{Level Cache}_{Level Cache}

Main

Memory

Memory _NVM_NVM

(9)

Memory Architecture Approaches

•

Lowest RAM density required

•

Lowest standby power

•

Minimum chip count, weight,

space

“Execute in Place” (XIP) Memory

“Store and Download” (SnD) Memory

Baseband R F DSP ARM* NVM RAM DSP Peripherals ARM* Peripherals Memory /B us Controller I$ I$ D$ RAM Code Data Flash RAM Working

Data flow in a I cache miss

Baseband R F DSP ARM* NVM RAM DSP Peripherals ARM* Peripherals Memory /B us Controller I$ I$ D$ RAM Data & Files NV Stora g e RAM Working Static

Data flow in a I cache miss

Shadow C o d e co p ie d a n d f ixed in p lace a t b o o t Working Static •

• Extra RAM density required or reduced Extra RAM density required or reduced

performance with demand paging

•

• Higher standby powerHigher standby power

•

• Higher software complexityHigher software complexity

•

• Single bus bottleneckSingle bus bottleneck

XIP Memory Shipping in 95% of Handsets

(10)

Subsystem Architecture Comparison

+

Low System Complexity

Code and Data Integrity, Simple Software

+

Low Power (Energy)

Code Execution Power in System Standby

--

/=

Fast File System Performance

File Write, Database, Multimedia file

+

Fast Code Performance

Multimedia, Java, Paging Impacts, Boot

=

Low Cost

Bill of Materials, Max User Available RAM

XIP over

SnD

Values

(11)

Next Steps: Extending the Benefits of an XIP

-

-based Memory Subsystem

based Memory Subsystem

y

Deliver the best XIP performance & data

storage performance

–

Higher performance XIP

–

Increased bus frequency, Flash DDR

–

Pipelined interface

–

Increased write speeds > 4 Megabits/sec

–

Optimized total subsystem solutions

y

Developing an array of solutions to make

mobile systems more secure

(12)

SnD

Enables Unauthorized Entry Points

Most viruses overwrite RAM in an unauthorized manner

Code executed directly from NOR Flash Code executed from RAM

XIP

SnD

Baseband R F DSP ARM* NVM RAM DSP Peripherals ARM* Peripherals Memory /B us Controller I$ I$ D$ RAM Code Data Flash LP SDRAM (Optio na l) WorkingWorking Static Baseband R F DSP ARM* NVM RAM DSP Peripherals ARM* Peripherals Memory /B us Controller I$ I$ D$ RAM Boot/ Comm Data & Files DI SK LP SDRAM Working Static Shadow Sh ado w e d /p ag ed cod e in v u lner ab le to modific a ti ons NOR

XIP foundation eliminates opportunity of

intercept while writing to RAM

Code Storage Memory = Execution Memory

(13)

Optimal Wireless Memory System

LPSDRAM

PSRAM

SRAM

Data Flash

Data Flash

Code NOR

Flexibility to Meet Different Phone Price Points

SRAM/PSRAM

PSRAM/LPSDRAM

LPSDRAM

Intel

Intel StrataFlashStrataFlash®® Wireless Memory

Wireless Memory

Data Flash

Card Slot

Intel

Wireless Memory

Scalable from Low to High

Intel

(14)

y

Evolution of Memory Requirements

y

(15)

’

08 Consumer Mobile Mass Storage

Target Density

Storage

Price Point

1 GB

0.1 GB

10 GB

100 GB

$1

$10

$100

Notebook PC

MLC NOR/NAND

≤

1.0

”

HDD

1.8

”

HDD

Volume Handset

High End MP3

Cards

HH Video Game

Digital Camcorder

(16)

Usage of SFF HDD in Handheld Systems

y

Power, vibration & environment inherent issues with rotating

media

y

Successful implementations focus on media storage

–

Large media files (MP3, MPEG4) are buffered into RAM and

HDD shut down

–

XIP code & system data in MLC NOR complements large

media storage in SFF

(17)

HDD in Handset Implementation

Solutions Scale High to Low

1T RAM

LP DRAM

MLC NOR

Data

Flash

Flash

Card Slot

MLC

NOR

LP DRAM

LP DRAM

MLC NOR

SFF HDD

1T/6T RAM

MLC NOR

Code + Key Data: OS,

Driver, Applications plus

Key System Data and

Databases

Media Data: Large file

data such as MPEG4

video, MP3 songs

RAM: Working system

memory & media data

buffered from HDD

HDD and MLC NOR Complementary

Solutions in Media

(18)

CE

-

ATA Industry Workgroup

y

Consortium focused on defining a standard interface for storage

devices

optimized for handheld and consumer electronics applications

y

Led by major industry

-

leading consumer electronics, storage and

semiconductor companies

–

Promoter Companies include Hitachi, Intel, Marvell, Nokia, Seaga

te and

Toshiba

y

(19)

y

Evolution of the Memory Subsystem

y

(20)

y

Visibility for scaling of

floating gate clear to 32 nm

y

Forms high

“

hurdle

”

for

new technologies to leap

1986/1.5

µ

m

1988/1.0

µ

m

1991/0.8

µ

m

1993/0.6

µ

m

1996/0.4

µ

m

1998/0.25

µ

m

2000/0.18

µ

m

2002/0.13

µ

m

2004/90n

m

“

Moore

’

s Law

”

Continues with FG NVM

2006/65n

m

2008/45n

m

90 nm cell is 1/476

thth

of

1.5

(21)

Near

-

term Candidates for Alternative

Memory

y

Three leading

alternative memories

–

Potential for

mainstream adoption

within 3 to 5 years

–

All are nonvolatile

execution

memories

y

But, no credible

technology challenger

to Flash through 2010

(22)

Attribute Fit to Requirements

Applied Electric Field Moves Center Atom

Data Storage Region Amorphous Chalcogenide Hea ter Poly Crystalline

OUM

MRAM

FeRAM

y

Execution

y

System storage

y

Embedded

y

Cell

≅

1.5 to 20 F

²

y

Fast read /

medium

write

y

Unlimited read, 10

1212

y

High performance

working memory

y

Execution & RAM

y

Cell

≅

16 –

16

–

40 F²

40 F

²

y

Fastest read/write

y

Unlimited R/W cycles

y

Low density

storage &

execution

y

Embedded

y

Cell

≅

12

-

25 F

²

y

Fast read/write

y

<10

99

read cycles

Application Fit

Key Attributes

(23)

Evolution of Future Handset Storage

y

Floating Gate and SFF

HDDs

have clear scaling path

y

Other new alternatives are longer term for mainstream

adoption (>3 to 5 years)

y

Promise new attributes @ new price points

FG Memory

“

Seek and Scan

”

MEMS

Cost of 1

st

MB

Multi

-

Layer Memory

(24)

Vision for Future

(25)

Memory Subsystem Evolution

1T RAM 1T RAM LP DRAM LP DRAM MLC NOR MLC NOR Data Data Flash Flash Card Slot Card Slot Card Slot Card Slot MLC MLC NOR NOR

Solutions Scale High to Low

1T/6T RAM

MLC NOR

2005

1T RAM 1T RAM LP DRAM LP DRAM MLC NOR MLC NOR Data Data Flash Flash Card Slot Card Slot Card Slot Card Slot MLC MLC NOR NOR LP DRAM LP DRAM MLC NOR MLC NOR SFF HDD SFF HDD 1T/6T RAM 1T/6T RAM MLC NOR MLC NOR

Faster 4+ Mb/sec

write

Enhanced security

solutions

High performance

XIP DDR Flash

(26)

Future Technology Vision

xRAM xRAM Card Slot Card Slot Card Slot Card Slot OUM OUM xRAM xRAM OUM OUM MEMS? MEMS? MLM? MLM? Integrated Integrated OUM OUM

Solutions Must Scale High to Low

(27)

Summary & Conclusions

y

XIP MLC NOR is at the core of the best

wireless memory subsystems

–

Best solution scales across the wide range

of needs

y

Intel extending memory solution with

higher performance, increased security

y

SFF HDD complements XIP NOR in

media

-

intensive applications

y

Phase change memory best candidate

for near

(28)