Nano open house Paolo Gargini

(1)

I n t e l N a n ot e ch nology

Vir t u a l Ope n H ou se

1

Intel

Nanotechnology

Overview

Paolo Gargini

Chairman ITRS

Director of Technology Strategy

Intel Fellow

(2)

I n t e l N a n ot e ch nology

2

Agenda

Nanotechnology: Origins and Myths

Geom etrical Scaling

Equivalent Scaling

I nnovation

Beyond CMOS

(3)

I n t e l N a n ot e ch nology

3

The Nanoscale

10

-

3

m = 1 Millim eter

10

-

9

m = 1 Nanom eter

10

-

6

m = 1 Microm eter

(4)

I n t e l N a n ot e ch nology

4

Scaling down the MOSFET design has

worked well up to current commercial size

devices sizes, but when MOSFETs are

fabricated below

100 nanometers in size,

certain factors may

inhibit their usefulness.

One hundred nanometers, or 0.1 micron, is

often called the

“0.1 micron barrier”.

Beyond

this barrier, many scientists believe that

new

devices will need to take the place of the

MOSFET. (1994 NTRS)

The MITRE Corporation, July 1996

Is 100nm the Ultimate Limit of CMOS?

(5)

I n t e l N a n ot e ch nology

5

Many investigators in the field of

next-generation electronics project that as the

smallest features on mass-produced

transistors shrink from their present length of

250nm to

100nm and below, the devices will

become more difficult and costly to fabricate.

The MITRE Corporation, March 1997

Is Cost the Ultimate Limit of CMOS?

(6)

I n t e l N a n ot e ch nology

6

National Nanotechnology

Initiative (NNI)

“

My budget supports a major new National Nanotechnology

Initiative, worth $500 million.

…

the ability to manipulate

matter at the atomic and molecular level. Imagine the

possibilities: materials with ten times the strength of steel an

d

only a small fraction of the weight

--

shrinking all the

information housed at the Library of Congress into a device

the size of a sugar cube

--

detecting cancerous tumors when

they are only a few cells in size. Some of our research goals

may take 20 or more years to achieve, but that is precisely

why there is an important role for the federal government.

”

----

President William J. Clinton

January 21, 2000

California Institute Of Technology

(7)

I n t e l N a n ot e ch nology

7

Nanothechnology Working

Definition

Nanotechnology refers to any application of

Science that deals with elements between

100 nanometers and a tenth of a nanometer

In size, in which size is critical to the

(8)

I n t e l N a n ot e ch nology

8

Word

-

wide Nanotechnology Funding

(M$)

4 6 5

1 0 0 8 6

6 9 8 7

4 5 4 7

2 7 8 0

1 7 5 8

1 0 5 6

4 3 2

3 0 9 9

2 4 4 0

1 7 6 7

1 0 2 2

7 0 2

6 2 4

4 3 2

8 4 9

7 7 0

6 9 7

4 6 6

2 7 0

2 5 5

1 1 6

8 0 0

5 5 0

3 8 0

1 1 0

9 6

8 3

7 0

8 0 0

7 2 0

2 4 5

1 5 7

1 3 5

1 2 0

Cu m

Tot a l

USA

Ot h e r s

Ja pa n

6 5 0

4 0 0

2 2 5

2 0 0

1 7 9

1 5 1

1 2 6

W .Eu r ope

2 0 0 4

2 0 0 3

2 0 0 2

2 0 0 1

2 0 0 0

1 9 9 9

1 9 9 7

Re gion

(9)

I n t e l N a n ot e ch nology

9

World

-

wide Nanotechnology $

Nanotechnology Funding

0

500

1000

1500

2000

2500

3000

3500

1997 1999 2000 2001 2002 2003 2004

Year

M

illio

n

$

W.Europe

Japan

Others

USA

Total

(10)

I n t e l N a n ot e ch nology

10

10000

1000

100

10

1

0.1

0.01

Micron

Nano

meter

-

-1970

1980

1990

2000

2010

2020

Microelectronics

Sub-micron

100nm is Not the Ultimate Limit of

CMOS!

Nanotechnology

Gate Width

YEAR

LSI

ULSI

NSI

Nano Scale Integration

(11)

I n t e l N a n ot e ch nology

11

The Law that Never Existed!

M oore ’s Se c ond La w

Cost of Fa

b

$60B

$50B

$40B

$36B

$20B

$10B

$0B

1992

1995

1998

2001

2004

2007

2010

M oore ’s Se c ond La w

Cost of Fa

b

$60B

$50B

$40B

$36B

$20B

$10B

$0B

(12)

I n t e l N a n ot e ch nology

12

Cost is Not the Limit of CMOS!

0.04

0.05

0.04

$B/kwpm

30

-

35

~77 (200mm

-

-equivalent)

equivalent)

40

20

Fab capacity,

kwpm

3

2

0.9

Fab cost, $B

(13)

I n t e l N a n ot e ch nology

13

>60X Transistor Cost Drop from 350nm to

90nm Node

(Source: Intel ‘03)

>60X Transistor Cost Drop from 350nm to

90nm Node

(Source: Intel

‘

03)

Cost/Transistor Normalized to 130nm Node Cost/Transistor Normalized to 130nm Node

Cost/Transistor Normalized to 130nm Node

2003

2001

1999

1997

1995

0.1

1.0

10.0

100.0

350nm

250nm

180nm

130nm

90nm

Technology Node/Introduction Year

N

o

rmalized Cos

t/Transistor

Cost per Total Trans 25% Savings/Year 35% Savings/Year 40% Savings/Year

(14)

I n t e l N a n ot e ch nology

14

The Era of

(15)

I n t e l N a n ot e ch nology

15

With respect to the factor contributed by Device and Circuit

Cleverness, however, the situation is different.

We are approaching a limit that must slow the rate of progress

I see no reason to expect the rate of progress

In the use of smaller dimensions in complex

Circuits to decrease in the near future.

Gordon Moore, IEDM

1975

(16)

I n t e l N a n ot e ch nology

16

Moore

’

s Law and Scaling Laws

Convergence

50% AREA READUCION

GENERATION TO GENERATION

50%

=> 30% LINEAR FEATURE REDUCTION

0.5 = 0.7

Year 0=1X

Year 1

(17)

I n t e l N a n ot e ch nology

17

Worldwide Transistor Production

1000000 10000000 1E+08 1E+09 1E+10 1E+11 1E+12 1E+13 1E+14 1E+15 1E+16 1E+17 1E+18

1955 1957 1959 1961 1963 1965 1967 1969 1971 1973 1975 1977 1979 1981 1983 1985 1987 1989 1991 1993 1995 1997 1999 2001

Units

There's no slowing of

Moore's Law here!

[ Transistors ]

Source: VLSI Research

(18)

I n t e l N a n ot e ch nology

18

Average Transistor Price by Year

Nearly 7 Orders Of Magnitude Reduction in Price/Transistor

0.0000001

0.000001

0.00001

0.0001

0.001

0.01

0.1

1

10

'68 '70 '72 '74 '76 '78 '80 '82 '84 '86 '88 '90 '92 '94 '96 '98 '00 '02

100 Nanodollars per transistor !

Source: WSTS/Dataquest/Intel, 3/04

(19)

I n t e l N a n ot e ch nology

19

Transistor Trade-offs

F

Max

= I

DSat

/ V

DD

C

ox

I

DSat

~1

µ

C

ox

(W)(V

DD

–V

T

)

2

Lg

Power= V

DD

2

C

ox

F

Max

S

D

G

Lg

W

Increase Cox

=>Reduce

t

ox

Reduce

Lg

Reduce

V

DD

ε

o

ε

s

(20)

I n t e l N a n ot e ch nology

20

Gate Oxide Scaling

1

10

1990

1995

2000

2005

Gate Oxide

Thickness

(nm)

1

10

1.2 nm

90nm

.13um

.18um

.25um

.35um

Generation

I

DSat

1

µ

(V

DD

–V

T

)

2

Lg

W

ε

o

ε

s

1

t

ox

~

(21)

I n t e l N a n ot e ch nology

21

Transistor Performance

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1990

1995

2000

2005

Drive

Current

(mA/um)

1

10

Supply

Voltage

(V)

NMOS

PMOS

1.2V

90nm

.13um

.18um

.25um

.35um

Generation

I

DSat

1

µ

(V

DD

–V

T

)

2

Lg

W

ε

o

ε

s

1

t

ox

~

(22)

I n t e l N a n ot e ch nology

22

Gate Delay Trend

100nm

F

Max

= I

DSat

/ V

DD

C

ox

(23)

I n t e l N a n ot e ch nology

23

0.35

Μ

Gate

Salicide

Spacer

Salicide

The Incredible Shrinking

Silicon Technology in the 90s

µ

0.25

Salicide

Gate

Spacer

Salicide

0.18

µ

Gate

SpacerSpacer

Salicide

1995

1997

1999

(24)

I n t e l N a n ot e ch nology

24

Process Name

Px60

P1262

P1264

P1266

P1268

Lithography

130nm 90nm

65nm

45nm

32nm

Gate Length

70nm

50nm

35nm

25nm

18nm

Wafer (mm) 200/300

300

1

st

Production

2001

2003

2005

2007

2009

Intel's Logic Technology

Evolution Continues

Moore's Law continues!

Intel continues to introduce a new

technology generation every 2 years

(25)

I n t e l N a n ot e ch nology

25

50nm

100nm

Transistor for

90nm

-

node

Gate oxide=1.2nm

Source: Intel

Influenza virus

Source: CDC

Nanotechnology Today

Example of today’s technology: 50 nm transistor dimension

Intel

Intel 2003 Silicon Nanotech Product

Revenue >$20B

(26)

I n t e l N a n ot e ch nology

26

50nm

But is this really

Nanotechnology

(27)

I n t e l N a n ot e ch nology

27

CMOS Future Directions

??/2-3year

New Devices

2010-20XX

2X Performance/2-3year

Integrated Solutions

2000-2014

70%/2-3year

70% / 2-3year

Equivalent Scaling

2005-2014

1970-2004

Traditional Scaling

Features

Source: ITRS 7/11/1998

(28)

I n t e l N a n ot e ch nology

28

The Era of

(29)

I n t e l N a n ot e ch nology

29

The Ideal MOS Transistor

Fully Surrounding

Metal Electrode

High-K

Gate Insulator

Fully Enclosed,

Depleted

Semiconductor

Band Engineered

Semiconductor

Low Resistance

Source/Drain

Drain

Source

(30)

I n t e l N a n ot e ch nology

30

New Transistor Trade-off

I

DSat

~1

µ

C

ox

(W)(V

DD

–V

T

)

2

Lg

S

D

G

Lg

W

Increase Cox

Reduce

Lg

µ

Increase

µ

ε

o

κ

s

t

ox

(31)

I n t e l N a n ot e ch nology

31

R

®

Gate Dielectric Scaling

1

2

3

Tox equivalent (nm)

4

8

12

Monolayers

4

0

1999

2001

2003

2005

1997 NTRS

P.Gargini

(32)

I n t e l N a n ot e ch nology

32

Gate Oxide Scaling

1

10

1990

1995

2000

2005

Gate Oxide

Thickness

(nm)

1

10

1.2 nm

Thinner gate oxide increases transistor performance

90nm

.13um

.18um

.25um

.35um

Generation

Silicon substrate

1.2nm SiO

₂

Gate

(33)

I n t e l N a n ot e ch nology

33

The Next Step Towards Equivalent

Scaling: High

-

k Dielectric

Silicon substrate

Gate

3.0nm High-k

Silicon substrate

1.2nm SiO

₂

Gate

November 4

th

, 2003

High-k

1.6x

< 0.01x

90nm process

1.0x

Capacitance:

Leakage:

(34)

I n t e l N a n ot e ch nology

34

Gate Dielectric Scaling (High

-

K)

1

10

1990

1995

2000

2005

Gate Dielectric

Thickness

(nm)

1

10

1.2 nm

Thinner equivalent gate oxide increases transistor performance

90nm

.13um

.18um

.25um

.35um

Generation

2010

K=

3X

K

D

K=

5X

K

D

(35)

I n t e l N a n ot e ch nology

35

Equivalent Scaling

plus

(36)

I n t e l N a n ot e ch nology

36

Transistor Strain

Techniques

D

G

S

D

G

Tensile Si

₃

N

₄

Cap

S

D

G

Selective SiGe S-D

Graded SiGe Layer

Biaxial

Tensile Strain

Uniaxial

Compressive Strain

for PMOS

Uniaxial

Tensile Strain

for NMOS

Traditional Approach

Intel's 90nm Technology

(37)

I n t e l N a n ot e ch nology

37

Strained Silicon Transistors

Normal Silicon Lattice Strained Silicon Lattice

Current Flow

Normal

electron

flow

Faster

electron

flow

(38)

I n t e l N a n ot e ch nology

38

Mobility Innovation

SiGe

Strained

P

-

Channel

Transistor

High Stress

Film

Strained

N

-

Channel

Transistor

(39)

I n t e l N a n ot e ch nology

39

40

60

80

100

120

140

0

0.2

0.4

0.6

0.8

1

1.2

E

EFF

(MV/cm)

Universal Hole

Mobility

M

o

b

ilit

y

c

m

2

/ (

V

*S

e

c

)

This work

Ref. 3

Ref. 2

Hole Mobility as a Function of

Vertical Effective Field

(40)

I n t e l N a n ot e ch nology

40

65nm Process

-

Transistor

Strained silicon enhanced for

perform ance and power

efficiency

35nm

(41)

I n t e l N a n ot e ch nology

41

1

10

100

1000

0.2

0.4

0.6

0.8

1.0

1.2

I

ON

(mA/um)

I

OFF

(nA/um)

PMOS

NMOS

90 nm

2002

2004

65 nm

2004

1.0 V

Improved Transistor Performance by

Use of Nanotechnology

6 5 n m t r a n sist or s in cr e a se dr ive cu r r e n t 1 0

-

1 5 % w it h e n h a n ce d st r a in

(42)

I n t e l N a n ot e ch nology

42

1

10

100

1000

0.2

0.4

0.6

0.8

1.0

1.2

I

ON

(mA/um)

I

OFF

(nA/um)

PMOS

NMOS

90 nm

2002

2004

65 nm

2004

1.0 V

Reduced Transistor Leakage by Use

of Nanotechnology

6 5 n m t r a n sist or s ca n a lt e r n a t ive ly pr ovide ~ 4 x le a k a ge r e du ct io

n

N o ot h e r com pa n y h a s m a t ch e d t h e se pe r for m a n ce

-

le a k a ge

ca pa bilit ie s

Power

Saving

Feature

(43)

I n t e l N a n ot e ch nology

43

Process Name

Px60

P1262

P1264

P1266

P1268

Lithography

130nm 90nm

65nm

45nm

32nm

Gate Length

70nm

50nm

35nm

25nm

18nm

Wafer (mm) 200/300

300

1

st

Production

2001

2003

2005

2007

2009

Intel's Logic Technology

Evolution

Moore's Law continues!

Intel continues to introduce a new

technology generation every 2 years

(44)

I n t e l N a n ot e ch nology

44

Continuation of Moore

’

s Law

St r a in e d

Si

St r a in e d

Si

St r a in e

d Si

St r a in e d

Si

St r a in e d

Si

Ch a n n e l

P1 2 7 0

P1 2 6 8

P1 2 6 6

P1 2 6 4

P1 2 6 2

Px 6 0

P8 5 8

P8 5 6

Pr oce ss N a m e

3 0 0

2 0 0 / 3 0 0

2 0 0

W a fe r Size

( m m )

M e t a l

Poly

-

-silicon

silicon

Poly

-

-silicon

silicon

Poly

-

-silicon

silicon

Poly

-

-silicon

silicon

Poly

-

-silicon

silicon

Ga t e e le ct r ode

H igh

-

k

H igh

-

k

H igh

-

k

SiO

₂₂

SiO

₂₂

SiO

₂₂

SiO

₂₂

SiO

₂₂

Ga t e die le ct r ic

?

Cu

Al

I n t e r

-

con n e ct

2 2 n m

3 2 n m

4 5 n m

6 5 n m

9 0 n m

0 .1 3

µ

m

0 .1 8

µ

m

0 .2 5

µ

m

Pr oce ss

Ge n e r a t ion

2 0 1 1

2 0 0 9

2 0 0 7

2 0 0 5

2 0 0 3

2 0 0 1

1 9 9 9

1 9 9 7

1 st Pr odu ct ion

Potential candidate for introduction

Subject to change

Intel found a solution for

High-k

and metal gate

Intel found a solution for

High

-

k

and metal gate

(45)

I n t e l N a n ot e ch nology

45

30nm

Prototype

(IEDM2000)

20nm Prototype

(VLSI2001)

25 nm 15nm

15nm Prototype

(IEDM2001)

50nm Length

(IEDM2002)

65nm Node

2005

45nm Node

2007

90nm Node

2003

32nm Node

2009

22nm Node

2011

10nm Prototype

(DRC 2003)

CMOS device scaling continues for > decade

11nm node

2015

----2

013 –

2017

16 nm node

2013

7nm

5nm

3nm

8 nm node

2017

----2

003

–20

12 –

––

Evolution

Innovation

?

(46)

I n t e l N a n ot e ch nology

46

(47)

I n t e l N a n ot e ch nology

47

The Size of Things

• 1 meter (1m)

• 1 mm (10

-3

m)

• 1

µ

m (10

-6

m)

• 1 nm (10

-9

m)

• 1 pm (10

-12

m)

• 1 fm (10

-15

m)

Silicon Lattice (

λ

=0.54 nm)

Human hair (<100

µ

m)

Sub-100nm Transistor, 2000 production

193 nm -DUV lithography

Wavelength of light (< 1

µ

m)

Limit planar transistor (~20-30 nm)

Limit ideal transistor (5 nm)

(48)

I n t e l N a n ot e ch nology

48

Plate

S

Silicon

D

L

L~5.4A

~1.6nm

The End of CMOS Progress

(49)

I n t e l N a n ot e ch nology

49

Some Particle’s Properties

Mass

Charge

Ψ=Σ

κ

c

κ

ψκ

(50)

I n t e l N a n ot e ch nology

50

Summary

•

The Sem iconductor I ndustry entered the

Nano Scale

I ntegration

Era in the

year 2000

•

I ntel has fully

em braced Nanotechnology

as a m eans of

continuously enhancing perform ance and density while

reducing cost of Nanoelectronics I ntegrated Circuits

•

Reported results indicate that I ntel will continue to

lead

the

Sem iconductor I ndustry into the Nano Scale I ntegration Era.

•

Scaling

( Geom etrical

-

> Equivalent

-

> I nnovative)

will

continue,

facilitated by the availability of m ore

“

knobs

”

( e.g.,

high m obility, high

-

k, low

-

k, thin body, m ulti

-

gates, etc)

well into the next decade

•

I n

-

house

developed innovative devices addressing the

needs of the next decades will be reported today by

Ken

David, Director of Com ponent Research

•

Em erging Research Devices

potentially capable of

extending the I C industry beyond CMOS for im plem entation

in 15

-

20 years will be presented

George Bourianoff,

Manager of Em erging Research Technology

•

Moore

’

s Law is still alive and well and it will

continue for the next 15

(51)

I n t e l N a n ot e ch nology

51

52 Mbit SRAM Chips on 300 mm Wafer

120 billion transistors on one wafer!

Nanotechnology?

Do it with silicon

and

silicon technology!