ASMs, Implicit Verilog and One-hot Designs: The VITO approach

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Copyright by Mark Arnold, 2002

ASMs, Implicit Verilog and

One-hot Designs:

The VITO approach

Mark G. Arnold

University of Manchester Institute of

Science and Technology

Outline

Structure and Behavior

Algorithmic State Machines

Basic Intro to Verilog Portlist, input and output

always for (C-like) behavioral code Implicit Verilog

Blocking (=) and Nonblocking Assignment (<=) Wait for clock event @(posedge sysclk)

One-hot controllers

Verilog Implicit To One-hot (VITO) preprocessor

Examples Silly Power (XY₎

Structure and Behavior

Unit A Unit B

Structure

How to build system?

Ex: Unit A is connected to Unit B

Behavior

What does system do?

Ex: What algorithm does unit A use? Algorithmic State Machine is one way. Behavioral HDLs are another:

Verilog or VHDL

STATE_NAME

Algorithmic State Machine (ASM)

… … other states

Rectangles describe states. System clock (sysclk) determines when transitions occur. Nice to give the state a name.

STATE_NAME

Moore action

Algorithmic State Machine (ASM)

Inside of rectangle are commands that happen anytime the state is entered (Moore)

STATE_NAME

cond 1

0

Moore action

Algorithmic State Machine (ASM)

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STATE_NAME

cond 1

0

Moore action

Mealy action

Algorithmic State Machine (ASM)

Optional oval comes after diamond. It says commands that happen anytime only when the state is entered and the condition is true. (Mealy)

STATE_NAME

cond 1

0

Moore action

Algorithmic State Machine (ASM)

Let’s ignore ovals, and concentrate on Moore machines.

Verilog and VHDL several kinds of assignment:

Evaluate b Change a Blocking assignment Now Now a = b;

Nonblocking assignment Now Future a <= b;

Nonblocking assignment is a better model of how clocked flip flops work. Let’s use this in an ASM chart:

Kinds of Assignments

Silly Example

Silly Machine sysclk

reset

/ a / b 2 2

Structure Two input ports:

sysclk is the system clock reset (ignored for the moment) Two output ports:

a (two bits wide) b (two bits wide)

Silly Example

a <= b b <= a

a <= 1 b <= 3

INIT

SWAP

reset

/ a / b 2 2

Behavior: Two states:

INIT initializes a and b

SWAP interchanges them

Silly Example

a <= b b <= a

a <= 1 b <= 3

INIT

SWAP

reset

/ a / b 2 2

What is the output ?

a b

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Silly Example

a <= b b <= a

a <= 1 b <= 3

INIT

SWAP

reset

/ a / b 2 2

a b

INIT x x SWAP 1 3

Silly Example

a <= b b <= a

a <= 1 b <= 3

INIT

SWAP

reset

/ a / b 2 2

a b

INIT 3 1

Silly Example

a <= b b <= a

a <= 1 b <= 3

INIT

SWAP

reset

/ a / b 2 2

a b

INIT 3 1

SWAP 1 3 ...

Silly Example

a = b b = a

a = 1 b = 3

INIT

SWAP

reset

/ a / b 2 2

Blocking = doesn’t work:

a b

INIT 3 33 SWAP 33 3 ...

Silly Example

a = b b = a

a = 1 b = 3

INIT

SWAP

reset

/ a / b 2 2

Blocking = doesn’t work:

a b

INIT 3 33 SWAP 33 3 ... VITO requires <= not =

Copyright by Mark Arnold, 2002 module example(sysclk,reset,a,b);

endmodule

Start with the structure.

The portlist shows all the inputs and outputs

Silly Example in Implicit

Silly Example in Implicit Verilog

Verilog

reset

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input sysclk,reset;

endmodule

Have to specify which ones are inputs...

Silly Example in Implicit

Silly Example in Implicit Verilog

Verilog

reset

/ a / b 2 2

input sysclk,reset; output [1:0] a,b;

endmodule

and outputs. The [1:0] means two bits wide.

Silly Example in Implicit

Silly Example in Implicit Verilog

Verilog

reset

/ a / b 2 2

input sysclk,reset; output [1:0] a,b; reg [1:0] a,b;

endmodule

The outputs are generated in registers that are local to the state machine .

Silly Example in Implicit

Silly Example in Implicit Verilog

Verilog

reset

/ a / b 2 2

input sysclk,reset; output [1:0] a,b; reg [1:0] a,b; always

begin

end endmodule

always is a infinite loop used for behavioral modeling of hardware; begin end similar to { } in C

Silly Example in Implicit

Silly Example in Implicit Verilog

Verilog

begin

@(posedge sysclk); //INIT

In implicit style, each state starts with @(posedge sysclk)

Silly Example in Implicit

Silly Example in Implicit Verilog

Verilog

INIT

begin

@(posedge sysclk); //INIT

@(posedge sysclk); //SWAP

Sequential execution means implicit state transitions always handles the loop at the bottom

Silly Example in Implicit

Silly Example in Implicit Verilog

Verilog

INIT

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begin

@(posedge sysclk); //INIT a <= 1;

b <= 3;

@(posedge sysclk); //SWAP

The <= means non-blocking assignment: 1 goes into a and 3 goes into b at the rising edge of next clock

Silly Example in Implicit

Silly Example in Implicit Verilog

Verilog

a <= 1 b <= 3

INIT

SWAP

begin

@(posedge sysclk); //INIT a <= 1;

b <= 3;

@(posedge sysclk); //SWAP a <= b;

b <= a;

Non-blocking assignment allows the parallel swap that takes effect at the next clock

Silly Example in Implicit

Silly Example in Implicit Verilog

Verilog

a <= b b <= a

a <= 1 b <= 3

INIT

SWAP

For many mathematical algorithms, WHILE is natural

Same condition tested from two states: From entry state

From bottom state of loop

Advantage: don't describe condition twice

The wonderful WHILE

Goal:

Compute

x

y_{= x * x * … * x}

using a loop y times

Special case: x0_{= 1 taken care of by WHILE}

Ports:

x,y input values (8 bits each) p output product (8 bits) sysclk system clock reset resetting signal

Internal register:

c local loop counter

Example of machine needing WHILE

{

c =0;

p =1;p =1;

while( while(c!=yc!=y))

{ {

c =c+1;

p =p*x; p =p*x;

}

while(1)

{

}

Example of machine needing WHILE

Compute

x

y = x * x * … * x using a loop y times

Here’s this algorithm in C:

Compute

x

For implicit Verilog, Need an always begin end to start behavioral code

always begin

c =0;

p =1;p =1;

while( while(c!=yc!=y))

begin begin

c =c+1;

p =p*x; p =p*x;

end

while(1)

begin

end

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Example of machine needing WHILE

Compute

x

Need @(posedge …) for each state

always

Example of machine needing WHILE

Compute

x

Need @(posedge …) for each state

Need <= rather than = (careful: <= not same as = )

GREEN

Example of machine needing WHILE

always

GREEN

Example of machine needing WHILE

always Here’s where VITO comes in

Copyright by Mark Arnold, 2002 \/ D

Q

Example one-hot controller

GREEN

With the one-hot method,

each state gets a flip flop Copyright by Mark Arnold, 2002

\/ D Q

Example one-hot controller

GREEN

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Copyright by Mark Arnold, 2002 \/ D

Q

\/ D Q

Example one-hot controller

GREEN p <= 1

c <= 0

c!=y BLACK

RED

WHITE

BLUE 1

0

c <=c+1

p <= p*x

Joining of two possible

transitions require OR gate Copyright by Mark Arnold, 2002

c!=y

\/ D Q

DEMUX 0 1

Example one-hot controller

GREEN p <= 1

c <= 0

c!=y BLACK

RED

WHITE

BLUE 1

0

c <=c+1

p <= p*x

Decision uses a demux:

c!=y

\/ D Q

DEMUX 0 1

Example one-hot controller

GREEN p <= 1

c <= 0

c!=y BLACK

RED

WHITE

BLUE 1

0

c <=c+1

p <= p*x

Decision uses a demux: no more than one output active

Truth Table for Demux

in c!=y out0 out1 0 0 0 0 0 1 0 0 1 0 1 0 1 1 0 1

c!=y

\/ D Q

\/ D Q DEMUX 0 1

Example one-hot controller

GREEN p <= 1

c <= 0

c!=y BLACK

RED

WHITE

BLUE 1

0

c <=c+1

p <= p*x

When cond true, start loop

c!=y

\/ D Q

DEMUX 0 1

Example one-hot controller

GREEN p <= 1

c <= 0

c!=y BLACK

RED

WHITE

BLUE 1

0

c <=c+1

p <= p*x

BLUE follows unconditionally from WHITE;

c!=y

\/ D Q

DEMUX 0 1

Example one-hot controller

GREEN p <= 1

c <= 0

c!=y BLACK

RED

WHITE

BLUE 1

0

c <=c+1

p <= p*x

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Example one-hot controller

GREEN

All 5 flip flops need sysclk.

c!=y

Example one-hot controller

GREEN

Set BLACK, clear others with async reset signal

c!=y

Example one-hot controller

GREEN

c!=y

Example one-hot controller

GREEN

are mutually exclusive; they control datapath c!=y output

from datapath

Example datapath

datapath

always

Example datapath

datapath

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Example datapath

datapath

always

Example datapath

datapath

always

Example datapath

datapath

always

Example datapath

datapath

/

The busses are M bits wide

module vito_power(sysclk,reset,x,y,p); input sysclk,reset; input [`M:0] x,y; output [`M:0] p;

Verilog Implicit To One-hot

Verilog synthesis preprocessor Works with any synthesis tool Accepts implicit and explicit style Leaves explicit block(s) alone Converts implicit block(s) to one-hot Vendor independent, freely available

Where is VITO?

www.verilog.vito.com

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Verilog to synthesize Verilog source

synthesis tool

generate architecture unchanged

statements and comments

implicit

always

parser

generate controller

VITO

merge

VITO

Organization

Synthesis tool often successful in optimizing VITO

Comparison of different implicit design flows

Implicit tool Synopsys VITO

Synthesis tool Synopsys Synopsys

Optimization tool MINC MINC

Technology Vantis Vantis

CLBs 363 345

Comparison of explicit versus implicit for Power (xy₎

Style explicit implicit

Design entry graphic ASM textual Verilog

Tool VeriBest VITO

Synthesis tool VeriBest VeriBest

Technology Xilinx Xilinx

CLBs 337 323