S04 Silicon Nanotechnology 100%

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Silicon Nanotechnology

Ken David

Director, Components Research

Technology & Manufacturing Group

Intel Corp.

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Agenda

What is Nanotechnology?

Nanoscaling

Nonclassical CMOS

Novel Devices

Summary

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Agenda

What is Silicon Nanotechnology?

CMOS

Nanoscaling

Nonclassical

CMOS

Novel Devices

Summary

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Nanotechnology Definition

“

Research and technology development at the

atomic, molecular or macromolecular levels,

in the length scale of approximately

1

-

100 nanometer

range.”

Dr. Mike

Dr. Mike RocoRoco, National Science and Technology , National Science and Technology Council, February 2000

Council, February 2000

Intel

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Technology Scaling

10000 10000 10 10 1000 1000 100 100 10 10 1 1 0.1 0.1 0.01 0.01 Micron

Micron NanometerNanometer

1970 1980 1990 2000 2010 2020

Nominal feature size

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50nm

100nm

Transistor for

90nm

-

node

Gate oxide=1.2nm

Gate oxide=1.2nm

Source: Intel

Influenza virus

Source: CDC

Source: CDC

Nanotechnology Today

Example of today’s technology: 50 nm transistor dimension

Intel

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Scaling => Nanoscaling

Nearly 7 Orders Of Magnitude Reduction in Cost/Transistor

0.0000001 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10

'68 '70 '72 '74 '76 '78 '80 '82 '84 '86 '88 '90 '92 '94 '96 '98 '00 '02

$

Source: WSTS/Dataquest/Intel, 8/02

Source: WSTS/Dataquest/Intel, 8/02

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Silicon Nanotechnology Evolution

y

Continued CMOS Nanoscaling

-materials, lithography innovation

y

Implement Non-classical CMOS

- new architectures, new structures

y

Transition to Novel devices

-alternative state variables

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Agenda

CMOS Nanoscaling

Nonclassical

CMOS

Novel Devices

Summary

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Gordon

Typical

engineer.

CMOS

Nanoscaling

…

.Extending

Moore

’

s Law

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New Materials, Devices Extend Si

Scaling

Gate

Silicide Silicide added added

Channel

Strained Strained silicon silicon

Changes

Made

Future

Options

High

-

k

gate

dielectric

Transistor

Source: Source: Intel Intel PolySi Silicon PolySi Silicon Gate dielectric less than 3 atomic layers thick

Source: Intel

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New Materials, Devices Extend Si

Scaling

Metal lines

Al Cu

Insulating

dielectric

SiO

SiO22 SiOFSiOF CDO

CDO

(low

(low--k)k)

Changes

Made

Future

Options

Ultra

Low

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4x5 matrix

152 mm2_{, 4X}

Reflective Mask 100 nm contacts 1:1

100 nm contacts 1:1

100 nm Elbows 1:1 100 nm Elbows 1:1

200 mm Wafer 200 mm Wafer

80 nm Elbows 1:1 80 nm Elbows 1:1

24 x 32.5 mm2 _field

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Strained Silicon Transistors

Current Flow

Normal electron

flow

Faster electron

flow

Normal Silicon Lattice Strained Silicon Lattice

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Strained Silicon Transistors

Strained silicon benefits

• Strained silicon lattice increases electron and hole mobility in transistor channels

• Greater mobility results in 10-20% increase in transistor current flow (drive current)

• Increased drive current = increased transistor performance • Both NMOS and PMOS transistor performance improved

Strained silicon process

• Intel's strained silicon process is unique in the industry • No detriments to transistor short channel behavior or

junction leakage

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Transistor Strain Techniques

Traditional Approach

Intel's 90nm Technology

D G

S

S D

G

S D

G

Graded SiGe Layer Selective SiGe S-D Tensile Si₃N₄ Cap

Biaxial Tensile Strain

Uniaxial

Compressive Strain for PMOS

Uniaxial Tensile Strain

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High-K Gate Dielectric

Silicon substrate Gate

3.0nm High-k

Silicon substrate 1.2nm SiO₂

Gate

90nm process

1.0x 1.0x

High-k

1.6x < 0.01x Capacitance:

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Final film Reactant 1

Step 1

Step 2

Introduce reactant 2

Step 3

Step 4

High-K Gate Dielectric Formed Using

Atomic Layer Chemical Vapor

Deposition

• “Self-assembly process” ready for manufacturing

• Sequential introduction of precursors molecules

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High-K/Metal-Gate Achieved

Recording-Setting Performance

1.E-10 1.E-09 1.E-08 1.E-07 1.E-06 1.E-05 1.E-04 1.E-03 1.E-02

0 0.2 0.4 0.6 0.8 1 1.2 1.4

Vg (V)

Id (A/µ

m)

Vd=1.3V

Vd=0.05V

Ion = 1.5 mA/µm Ioff = 43 nA/µm

Lg = 80nm Toxe = 14.5A

1.E-10 1.E-09 1.E-08 1.E-07 1.E-06 1.E-05 1.E-04 1.E-03 1.E-02

0 0.2 0.4 0.6 0.8 1 1.2 1.4

Vg (V)

Id (A/µ

m)

Vd=1.3V

Vd=0.05V

Ion = 1.5 mA/µm Ioff = 43 nA/µm

1E-10 1E-09 1E-08 1E-07 1E-06 1E-05 1E-04 1E-03 -1.3 -1.1 -0.9 -0.7 -0.5 -0.3 -0.1 Vg (V) Id (A/µ m) Vd=0.05V Vd=1.3V

Ion = 693 µA/µm Ioff = 25 nA/µm

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Continuation of Moore’s Law

Process Name P856 P858 Px60 P1262 P1264 P1266 P1268 P1270

Channel Si Si Si Strained _Si Strained _Si Strained _Si Strained Si Strained Si 1st Production 1997 1999 2001 2003 2005 2007 2009 2011

Process

Generation 0.25µm 0.18µm 0.13µm 90 nm 65 nm 45 nm 32 nm 22 nm

Wafer Size (mm) 200 200 200/300 300 300 300 300 300

Inter-connect Al Al Cu Cu Cu Cu Cu ?

Gate dielectric SiO₂ SiO₂ SiO₂ SiO₂ SiO₂ High-k High-k High-k

Gate electrode Poly-silicon

Poly-silicon

Poly-silicon Metal Metal Metal

Introduction targeted at this time

Introduction targeted at this time _{Subject to change}_{Subject to change}

Source: Intel

Intel found a solution for

High-k

and metal gate

Intel found a solution for

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Agenda

Nanoscaling

Nonclassical CMOS

Novel Devices

Summary

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Transistor Architectures

Double-gate (e.g. FINFET)

(Non-Planar)

W

_Si

L

_g T_Si Isolation Gate 1 Gate 2 Source Drain

Tri-gate

(Non-Planar)

W

_Si

L

_g

T

_Si Gate 1 Gate 2 Gate 3 Source Drain L

Si T_Si

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Tri-Gate Transistor

Top Gate

Side Gate

Tri-Gate Conventional Planar Tri-Gate Planar Actual photo

30nm tri-gate transistor

Simulation

Cross-section of silicon channel shows much more current flow

(indicated by red) in tri-gate transistor than in planar

Source

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World Record Non-Planar Performance

Very high drive current at saturation, 1.23 mA/µm

1E-08 1E-07 1E-06 1E-05 1E-04 1E-03 1E-02

0 0.2 0.4 0.6 0.8 1 1.2 1.4 Gate voltage (Volts)

Drain current (amps/

µ

m)

Drain voltage=0.05V Drain voltage=1.3V

Tri-gate transistor exhibits excellent device

characteristics

Tri

-

gate transistor exhibits excellent device

characteristics

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Non-Classical CMOS

Source: Morales & Lieber, Science

Source: Morales & Lieber, Science 279, 208 (1998)279, 208 (1998) Silicon

Silicon NanowireNanowire Carbon

Carbon NanotubeNanotube

y

Many options including nanotubes/nanowires

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CMOS Device Scaling Demonstration

90nm Node

2003 _{65nm Node} 2005

50nm Length (IEDM2002)

30nm Prototype

(IEDM2000) _{20nm Prototype} (VLSI2001) 25 nm 15nm 45nm Node 2007 32nm Node 2009 22nm Node 2011 15nm Prototype 15nm Prototype (IEDM2001) (IEDM2001) 10nm Prototype 10nm Prototype (DRC 2003) (DRC 2003) 11nm node 2015 16 nm node

2013

TBD TBD 8 nm node

2017

Integration of nanotubes, nanowires onto

Si by end of this decade will extend device

scaling well into next decade

Integration of

nanotubes

,

nanowires

onto

Si

by end of this decade will extend device

scaling well into next decade

Si n

ano

wire

s??

TBD

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Agenda

What is silicon Nanotechnology?

Nano

Scaling

Non classical CMOS

Novel Devices

Summary

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Novel Devices

y

Many device options….

y

Compatibility with CMOS for evolutionary

introduction

y

Directed or self assembly of arrays???

–

Defect density or purity required….

y

Self correcting architectures??

•

Nanotechnology needs a richer suite of

functionality…

Collaboration between

industry, universities, and

government is essential

Collaboration between

industry, universities, and

government

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Novel Devices

What are we looking for?

y Required characteristics:

– Scalability

– Performance

– Energy efficiency

– Gain

– Operational reliability

– Room temp. operation

y Preferred approach:

– CMOS process compatibility

– CMOS architectural compatibility

Alternative state variables

y

Spin–electron, nuclear,

photon

y

Phase

y

Quantum state

y

Magnetic flux quanta

y

Mechanical deformation

y

Dipole orientation

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Intel Involved in University Research

Intel

-

supported Nanotechnology Research at Universities

California

Arizona

Florida Texas

Ireland Illinois

Israel Tennessee

Oregon

Colorado Ohio

New York

Mass

Intel engaged

in >300 SRC*

projects at

50 universities

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Agenda

Nano

Scaling

Non classical CMOS

Novel Devices

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Summary

y Nanotechnology is here today in “state of the art” high speed Si CMOS process technologies

y Si nanotechnology process scaling/convergence will continue indefinitely.

y New architectures will further extend silicon scaling.

y Novel technologies being investigated and may be integrated with silicon technology mid-next decade

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