Index of /intel-research/silicon

(1)

Future Perspective of

Non

-

Volatile Memory

Stefan Lai, PhD, Fellow IEEE

Intel Corporation

Vice President, Technology and Manufacturing Group

(2)

Why Non

(3)

Mobile Lifestyle: Data Anytime, Anywhere

Enterprise Enterprise

Richest Richest Experience Experience

Greatest Mobility Greatest Mobility

Internet

(4)

Computing is Going Mobile

Saturday

Sunday Friday

Thursday Wednesday

Tuesday

Plaza hotel

School

(5)

Memories for Mobility

y

y NonNon--volatile = low power: power down to save volatile = low power: power down to save power

power

y

y Low cost: one memory for program and data Low cost: one memory for program and data storage

storage

y

y ≠≠ magnetic hard disk: need solid state, low magnetic hard disk: need solid state, low power, rugged

power, rugged

y

(6)

Moore’s Law in NV Memory

y

y Moore’s Law will continue through innovation Moore’s Law will continue through innovation

–

– Process complexity will increase to address Process complexity will increase to address fundamental limits of physics

fundamental limits of physics y

y To maintain Moore’s Law cost learning curve, To maintain Moore’s Law cost learning curve, difficult to do it by transistor technology alone

difficult to do it by transistor technology alone

–

– New opportunity for new memory structures and new New opportunity for new memory structures and new materials

materials y

y Current mainstream NV memory technologies Current mainstream NV memory technologies of ETOX and NAND will continue to be the key

of ETOX and NAND will continue to be the key

technologies for more than 5 years out

technologies for more than 5 years out

y

(7)

Moore’s Law will Continue with

ETOX



Flash

y

y Currently shipping 8Currently shipping 8thth _{generation of ETOX}_{generation of ETOX}_®_®

flash memory in high volume

flash memory in high volume

–

– ~50% cell size reduction per generation~50% cell size reduction per generation

y

y Good visibility into 90 nm and 65 nm generationGood visibility into 90 nm and 65 nm generation

y

y Current projection shows scaling continues at Current projection shows scaling continues at 45 nm node but challenged to meet 50% goal

45 nm node but challenged to meet 50% goal

y

y Further innovation required to maintain cost Further innovation required to maintain cost learning curve

learning curve

y

y Industry trend: complex transistor structure to Industry trend: complex transistor structure to meet scaling challenges

(8)

1986 / 1.5µm 1988 / 1.0µm 1991 / 0.8µm 1993 / 0.6µm

1996 / 0.4µm 1998 / 0.25µm _{2000 / 0.18}µ_m _{2002 / 0.13}µ_m

5.4X

1986 / 1.5µm 1988 / 1.0µm 1991 / 0.8µm 1993 / 0.6µm

1996 / 0.4µm 1998 / 0.25µm _{2000 / 0.18}µ_m _{2002 / 0.13}µ_m 1986 / 1.5µm

1986 / 1.5µm 1988 / 1.01988 / 1.0µµmm 1991 / 0.81991 / 0.8µµmm 1993 / 0.61993 / 0.6µµmm

1996 / 0.4µm

1996 / 0.4µm 1998 / 0.251998 / 0.25µµmm _{2000 / 0.18}_{2000 / 0.18}µµ_m_m _{2002 / 0.13}µ_m

5.4X

ETOX

®

Technology Scaling

y

y 18 years and 8 Generations of ETOX18 years and 8 Generations of ETOX®® to 0.13 to 0.13 µµmm

Volume Production Year / Technology Generation

(9)

Example of Future Transistor

Source

Source

Drain

Gate

Source: Intel

Gate

Silicon

Drain

Source

Example of

Current Flash

Memory Cell

(10)

New Materials in Silicon

Technology

y

y The semiconductor industry has been The semiconductor industry has been addressing the performance and cost

addressing the performance and cost

issues by introducing new materials

–

– Tantalum pentoxide for DRAM storage dielectricTantalum pentoxide for DRAM storage dielectric

–

– Cobalt and Nickel for S/D formationCobalt and Nickel for S/D formation

–

– Copper and low k dielectric for interconnectCopper and low k dielectric for interconnect

–

– High K dielectric for transistor gateHigh K dielectric for transistor gate

y

y For nonFor non--volatile memories, new memory volatile memories, new memory materials provide new opportunities for

materials provide new opportunities for

further memory cost reduction

(11)

Review of New Memories

y

y Explosion of research and development on new Explosion of research and development on new memory technology and material

memory technology and material

y

y Scopes range from full scale manufacturing Scopes range from full scale manufacturing development to industrial labs to new startup

development to industrial labs to new startup

companies to university research

y

y Time frames range from product now to nano Time frames range from product now to nano technology research 10

technology research 10--20 years out20 years out

y

y No perfect memory, each has its own unique No perfect memory, each has its own unique challenge

(12)

Examples of new memory

technologies

(13)

FeRAM

y

y Operation Operation

y

y Selected PZT crystalline Selected PZT crystalline materials have bi

materials have bi--stable stable center atom

center atom

y

y Data is stored by Data is stored by

applying an voltage to applying an voltage to polarize the internal polarize the internal dipoles “Up” or “Down” dipoles “Up” or “Down”

y

y Reading by sensing the Reading by sensing the displacement current displacement current

y

y Fast read/write < 100 Fast read/write < 100 nSec

nSec

y

y Destructive read, limited Destructive read, limited number of read cycles number of read cycles due to fatigue

due to fatigue

y

y Very low power Very low power consumption consumption

Applied Electric Field Moves Center Atom

Perovskite Crystal Unit Cell

PZT (PbO,ZrO₂, TiO₂) Lead-Zirconate-Titanate

Di/Monovalent Metal Atoms Tetra/Pentavalent Atom

Oxygen Atoms

PZT Film Polarized Top Electrode

Bottom Electrode

E_Film E_App

E_Net = E_App- E_Film

(14)

y

y OperationOperation

y

y Cell is 1 MJT + 1 TransistorCell is 1 MJT + 1 Transistor

y

y Electric current switches the Electric current switches the magnetic polarity of sense layer magnetic polarity of sense layer

y

y Change in magnetic polarity Change in magnetic polarity sensed as resistance change in sensed as resistance change in tunnel junction

tunnel junction

y

y Non destructive readNon destructive read

y

y Very fast read/write Very fast read/write performance, < 10

performance, < 10 nSec nSec reported

reported

y

y Unlimited number of R/W Unlimited number of R/W endurance

endurance

y

y Relatively high write currentRelatively high write current

MRAM

(15)

Ovonics Unified Memory

Data Storage Region

Resistive Electrode Amorphous Chalcogenide Phase Change Material Heater Poly Crystalline y

y

y Chalcogenide material Chalcogenide material alloys used in re

alloys used in re-

-writable CDs and DVDs writable CDs and DVDs

y

y Electrical energy (heat) Electrical energy (heat) converts the material converts the material between crystalline between crystalline (conductive) and (conductive) and amorphous (resistive) amorphous (resistive) phases phases y

y Cell reads by Cell reads by

measuring resistance measuring resistance

y

y Non-Non-destructive readdestructive read

y

y ~10~101212 _{write/erase cycles}_{write/erase cycles} y

y Medium write powerMedium write power

y

y Relatively easy Relatively easy

(16)

Complex Metal Oxide RRAM

Poly Crystalline y

y Operation_Operation y

y PCMO material, PCMO material,

Complex metal oxide

studied for high temp

superconductivity

y

y Change in resistance Change in resistance with applied electric field

with applied electric field

y

y Low resistance with Low resistance with forward bias, high

forward bias, high

resistance when reverse

electric field applied

y

y Low field read by Low field read by

measuring resistance

(17)

Programmable Metallization Cell

y

y Operation_Operation y

y Silver “dissolved” in Silver “dissolved” in chalcogenide

chalcogenide

y

y Change in resistance Change in resistance

driving silver to form low

resistance path

y

y Reversible with reverse Reversible with reverse field

field

y

y Low field read with no Low field read with no disturb

disturb

y

y Very fast write and Very fast write and relatively low power

(18)

Resistance Polymer Memory

Poly Crystalline y

y

y Polymer material with Polymer material with special formulation

special formulation

y

y Change in resistance Change in resistance due to ionic transport

due to ionic transport

y

y Low resistance when Low resistance when ionic conductance paths

ionic conductance paths

formed, high resistance

when process is

reversed when paths

broken

y

y Low field read with no Low field read with no read disturb

(19)

Carbon Nanotube Switches

y

y Carbon nanotube Carbon nanotube

suspended in crossbar

architecture

y

y Electrostatic field attracts Electrostatic field attracts the nanotube and held

the nanotube and held

together by van der

Waals force

y

y Reverse bias repulse the Reverse bias repulse the wires

wires

y

y Reading by low vs high Reading by low vs high resistance

resistance

y

(20)

Molecular Memory

y

y Molecules in cross Molecules in cross point array

point array

y

y Change in electronic Change in electronic states in Redox

states in Redox

process with applied

voltage

y

y Memory state sensed Memory state sensed by charge

by charge

displacement

y

y More than 1 state can More than 1 state can be stored by design of

be stored by design of

molecule (up to 8

(21)

Molecular Tunnel Memory

y

Operation

y

y Molecules in cross Molecules in cross point array

point array

y

y Change in Change in

resistance with

applied electric field

y

y Memory state Memory state sensed by

sensed by

measured

resistance change

(22)

Ferroelectric Polymer Memory

CMOS Base Wafer

Interface Logic Sense Amps/ Interconnect Charge Pump Charge Pump Word line Polymer Layer

Bit line Bit line Bit line

Polymer Layer Word line Word line Insulator (polymer) Word line Polymer Layer

Bit line Bit line Bit line

Polymer Layer

Word line Word line

y

y Polymeric Ferroelectric RAM Polymeric Ferroelectric RAM (PFRAM)

(PFRAM)

y

y Polymer chains with a dipole Polymer chains with a dipole moment

moment

y

y Data stored by changing the Data stored by changing the polarization of the polymer

polarization of the polymer

between metal lines

y

y Zero transistors per bit of storageZero transistors per bit of storage

y

(23)

3D One Time Program Memory

y

y MultiMulti-layer one time -layer one time

programmable diodes at programmable diodes at

minimum lithography minimum lithography

dimensions dimensions

y

y Simplified architecture Simplified architecture with minimum number of with minimum number of

metal lines metal lines

y

y Zero transistor per cellZero transistor per cell

y

y Standard CMOS Standard CMOS

transistors under and transistors under and

outside array, process outside array, process

cost amortized over cost amortized over

multiple memory cells multiple memory cells

y

(24)

Millipede Memory

y

y Basic concept similar to punch Basic concept similar to punch cards

cards

y

y Thermally assisted, rewritable Thermally assisted, rewritable displacement media, PMMA displacement media, PMMA

y

y Large array of independently ZLarge array of independently Z- -axis controlled tips

axis controlled tips

y

y Low moving mass Low moving mass

y

y Direct point to point motion, no Direct point to point motion, no rotational latency

rotational latency

y

y Low power, no motors, actuators Low power, no motors, actuators

y

y High data transfer rates, High data transfer rates,

concurrent data transfer to/from concurrent data transfer to/from multiple tips

multiple tips

y

(25)

Spin Polarized E Beam Magnetic Memory

y

y Basic concept similar to Basic concept similar to Magnetic Hard Drive Magnetic Hard Drive

–

– Mechanical arm -Mechanical arm -> spin > spin polarized E Beam

polarized E Beam –

– Spinning Magnetic Media Spinning Magnetic Media - -> steered E Beam

> steered E Beam

y

y Much lower first read latency, Much lower first read latency, first access limited by E Beam first access limited by E Beam steering; fast read with E Beam steering; fast read with E Beam

y

y Lower power, no motor, no arm Lower power, no motor, no arm actuator

actuator

y

y No moving part, rugged, No moving part, rugged, vacuum space required vacuum space required

y

y Not as small or compact as all Not as small or compact as all solid state memories

(26)

A Simplified View

y

y All above memories can be divided into two All above memories can be divided into two broad categories:

broad categories:

1.

1. XX--Y addressable, limited by lithography and Y addressable, limited by lithography and follows Moore’s Law

follows Moore’s Law

2.

2. Seek and scan memory, no lithography, Seek and scan memory, no lithography,

limited by scan mechanism, size and density

of storage areas in storage medium

(27)

Breaking the scaling barrier

y

y Memory technologies requiring transistor switch will be Memory technologies requiring transistor switch will be limited in scaling

limited in scaling --> FeRAM, MRAM, diode switch scales > FeRAM, MRAM, diode switch scales better

better --> OUM, RRAM> OUM, RRAM

Ä

Ä Follows MooreFollows Moore’’s Law limited by transistor/diodes Law limited by transistor/diode

y

y Simple cross point switch with no transistor or diode Simple cross point switch with no transistor or diode more scalable: molecular memories

more scalable: molecular memories

Ä

Ä Continue MooreContinue Moore’’s Law beyond transistor ages Law beyond transistor age

y

y MultiMulti--layer memories have the potential to be lowest layer memories have the potential to be lowest cost for litho defined memory

cost for litho defined memory

Ä

Ä Drop below historical MooreDrop below historical Moore’’s Laws Law

y

y Seek and scan can be the lowest cost but involves new Seek and scan can be the lowest cost but involves new memory storage and sense mechanism

memory storage and sense mechanism

Ä

(28)

No transistor switch better than

transistor switch

Big

(29)

Small is not that small

y

y X-X-Y addressable memory is Y addressable memory is always limited by the limiting always limited by the limiting lithography steps: have to lithography steps: have to connect to the real world connect to the real world circuits

circuits

y

y Either self assembled circuits at Either self assembled circuits at the smaller geometry or new the smaller geometry or new innovative architecture

(30)

Breaking the scaling barrier

y

limited in scaling --> FeRAM, MRAM, diode switch scales > FeRAM, MRAM, diode switch scales better

Ä

y

Ä

y

cost for litho defined memory

Ä

y

Ä

(31)

Multi

-

layer is smaller

Level N+1: Antifuse, P-, P+, conductor, P+

(fill and antifuse made transparent) Matrix Confidential Level N+1: Antifuse, P-, P+, conductor, P+

(fill and antifuse made transparent) Matrix Confidential

Single Layer cell area =

Single Layer cell area =

4

4 λλ22

Multi Layer cell area =

4

4 λλ22_{/ N (number of}_{/ N (number of}

layers)

(32)

Breaking the scaling barrier

y

limited in scaling --> FeRAM, MRAM, diode switch scales > FeRAM, MRAM, diode switch scales better

Ä

y

Ä

y

cost for litho defined memory

Ä

y

Ä

(33)

Seek and Scan has best scaling

potential

(34)

Market Potential

(35)

Value of polymer or seek and

scan Memory

Log Read/Write Time (faster>)

Log Read/Write Time (faster>)

Cost (expensive>)

Disk Drives

Semi-Conductor

Memories

SRAM DRAM Polymer or seek

(36)

Value of New NV RAM

Log Write Time (faster >)

ROM Space ROM EPROM

Not in-system Changeable

Volatile Memory

Space

SRAM DRAM

New NV RAM Space

FeRAM OUM MRAM

Limited Unlimited Read Read Cycles Cycles

Flash Space

ETOX NAND

(37)

Unique Challenges of Non

-

Volatile

Memories

y

y Commonly accepted NV memory retention Commonly accepted NV memory retention time spec is 10 years

time spec is 10 years

y

y Retention is Retention is NEVERNEVER limited by the typical bits: limited by the typical bits: it is always limited by defect mechanisms

it is always limited by defect mechanisms

y

y Storage mechanisms must have high energy Storage mechanisms must have high energy barrier for long term stable retention

barrier for long term stable retention

y

y In most cases, the write mechanism may cause In most cases, the write mechanism may cause degradation to either the write mechanism

degradation to either the write mechanism

itself or to retention: giving limited cycling

capability

(38)

System Consideration

y

y The new memory technologies are not going to The new memory technologies are not going to be direct plug and play replacement of

be direct plug and play replacement of

conventional memory

y

y They may operate in different modes and may They may operate in different modes and may have higher error rate or higher defect density

have higher error rate or higher defect density

y

y To take best advantage, system architecture To take best advantage, system architecture should comprehend memory operation

should comprehend memory operation

y

y Error detection and error correction will be an Error detection and error correction will be an integral part of the future memories

(39)

Summary

y

y Moore’s Law will continue through innovation Moore’s Law will continue through innovation

–

– Process complexity will increase to address Process complexity will increase to address fundamental limits of physics

fundamental limits of physics y

y To maintain Moore’s Law cost learning curve, To maintain Moore’s Law cost learning curve, difficult to do it by transistor technology alone

difficult to do it by transistor technology alone

–

– New opportunity for new memory structures and new New opportunity for new memory structures and new materials

materials y

y Current mainstream memory technologies of Current mainstream memory technologies of ETOX and NAND will continue to be the key

ETOX and NAND will continue to be the key

technologies for more than 5 years out

(40)

Summary (continued)

y

y Many potential new memory technologiesMany potential new memory technologies

y

y Simple cross point memory scales better than Simple cross point memory scales better than transistor switch but will always be litho limited

transistor switch but will always be litho limited

y

y MultiMulti--layer cross point provides lowest cost layer cross point provides lowest cost opportunities following Moore’s Law

opportunities following Moore’s Law

y

y Seek and scan memories can break through the Seek and scan memories can break through the litho barrier and scales more than Moore’s Law

litho barrier and scales more than Moore’s Law

y

y System architecture integral part of memory System architecture integral part of memory system