Device Fabrication and Photovoltaic Measurements of Wire Arrays
5.3 Characterization of VLS-grown Samples
An SOI planar control doped by the same procedure as outlined above was sent to Solecon for spreading resistance depth profiling in order to assess the effectiveness of this procedure in attaining the doping profile we wanted. The results are shown in Fig. 5.1. We indeed see an n-type doping level of ≈1017 cm3 throughout the base, and a highly doped p-type emitter, with surface concentration near the bulk solubility of B in Si at the emitter diffusion temperature, extending several hundred nm into the Si.
5.2.3 Metallization
Finally, the sample edges were cleaved off to prevent macroscopic shunting, oxide was re- moved from the entirety of the samples with buffered HF (Transene), and contact was made to the back surface by immediately rubbing Ga/In onto the back of the sample and the sam- ple then bonded with Ag paste (SPI Supplies) to a piece of stainless steel to which electrical contact could be made with a probe tip. Contact was made to the front surface with a spot of Ga/In and an electrical probe tip. This led to the cell structure as depicted in Fig.
5.2. This method of contacting was used for convenience and was shown on homogeneously doped planar wafer samples to produce ohmic contacts of low resistivity (not shown).
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Figure 5.1. Spreading resistance depth profile of a control SOI wafer, indicating carrier concentration and type as a function of depth. Courtesy of Solecon Labs.
Figure 5.2. Schematic of VLS-grown wire cell, results from the characterization of which are presented in Fig. 5.3.
Figure 5.3. Light and darkJ-V scans for a VLS-grown, diffusion-doped cell. In this case, the device was≈0.42 cm2 in area, and exhibited aJsc of≈12 mA/cm2,Vocof 213 mV,F F of 33 %, and overall efficiency of 0.87 %. Note that this measurement was made with the wires still attached to their growth substrate, so a significant amount of the photoresponse may be from the substrate itself. Fig. (a) shows the light and darkJ-V response between -1 and +0.8 V. Fig. (b) is a more detailed look at the light J-V response in forward bias for the same cell.
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wherenis the diode quality factor. Doing this (not shown) yieldsn= 1.81 for this device.
This can then be used, with the same equation, to calculate an effective J0 - for this device J0 ≈1.3×10−4 A cm−2.
This is a very high value for dark current density, and also the cells are clearly suffering from shunting (compare the large current density passed in reverse bias in Fig. 5.3 with a cell that is not suffering from shunting as in Fig 5.7). Unfortunately, results to date do not distinguish whether the observed shunting is simply the result of poor contact formation, or something more fundamental related to the VLS catalyst or other impurities shunting the junction. Answering this question would be a key step forward in determining whether Ni- or Cu-catalyzed, VLS-grown Si wires can make a viable absorber material in a PV device.
The wires in this cell had diameters of less than 2μm. Given that they were grown in a pattern with 7μm pitch, if the wire pattern were perfect and all the wires grew vertically, in a top-down view the wires would only fill 6.4 % of the plane. The wires are attached to a Si substrate of low enough doping that the substrate itself exhibits a photoresponse (which was necessary in order to avoid having the substrate shunt the entire device. Independent PV measurements of the substrate material were made but are not shown here), but the photoresponse of the substrate is presumably severely degraded by the diffusion of Cu and potentially other metal impurities during the growth, diffusion and drive-in steps. In the limit that Jsc can be attributed entirely to the wires, the reason that this is not higher than 12 mA/cm2 may be due to the relatively low packing fraction of wires in this pattern.
One might expect that in that case Jsc should be even lower, but recent measurements by M. D. Kelzenberg (unpublished) have shown absorption in wire arrays that is several times higher than one might expect based on their geometric packing fraction alone. Also, the fidelity of this wire array, which was not perfect to begin with, was degraded during cell processing, leaving some wires pointing at angles other than normal to the substrate. If these wires were still in good electrical contact with the substrate, they might potentially benefit from being at an angle relative to the incident light. However, there is clearly a need to deconvolute wire response from the response of the growth substrate, and our group has recently reported on a technique that will allow for the fabrication and testing of substrate-free devices in the future. [119]
Also, if Fig. 5.1 is truly representative of the doping profile throughout the length of the wires, the emitter may be as thick as 400 nm, in a shell around the n-type wire core. In
2μm diameter wires, this would mean that the wire cores only fill≈2.3 % of the top-down area of the plane. Given that the bulk of the photoresponse comes from the wire cores, given the high emitter doping, and presumably large surface recombination, this may be limiting the ability of the device to deliver a large photocurrent. Growing wires with larger diameters and/or more tightly controlled, thinner emitters should improve this. Deposited, rather than diffused emitters, may be useful in order to obtain abrupt junctions where the emitter is not quite so highly doped. Also, amorphous Si emitters may be useful for enhanced surface passivation and to build voltage.
The wires were subjected to extended periods at very high temperatures during cell processing, as described above. On the other hand, the bulk of our TEM, nanoSIMS, and single-wire optical and electrical characterization has been on as-grown wires. It is possible that the extended, high temperature processing is damaging or degrading our wires in unanticipated ways, either because it is somehow damaging the Si crystal lattice itself, or because it is leading to diffusion of additional impurities into the Si. Our group is now looking at in-situ doping (which could be used to dope the core of the wires during growth), as well as rapid thermal processing (which might be used to form an emitter with a far briefer diffusion than is possible in our current, tube furnace setup) to attempt to reduce these potential effects.
It would also be useful to characterize the Si wires after the cell processing has been completed. This could be done with nanoSIMS to see if additional impurity species are present after the processing, as well as to examine whether the pn junctions in the wires are really as we would expect from our SOI analogs. Also useful would be TEM analysis of processed wires, to look for damage to the crystal structure. In order to gain a thorough understanding of our device performance, independent of the difficulties associated with making robust contacts to large-area devices from grown wires, as well as to understand whether the observed shunting is intrinsic to the wires or simply the result of poor contact formation, PV measurements of single, radial pn junction wires could be invaluable. These measurements have recently been conducted by Tian et al. on wires grown from SiH4 precursors, to great effect. [129]
An additional confounding factor is that these wire array devices, while ostensibly Cu- catalyzed, in fact have likely been affected by significant cross-contamination of metal cat- alyst types within our APCVD reactor. Until recently we had not taken enough care to
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use separate tubes and sample boats for each catalyst type, and therefore it is likely that even in the Cu-catalyzed samples there is a significant amount of Au and Ni present. How- ever, a first attempt at fabrication of cells from Ni-catalyzed wires with our new processing protocol, using separate growth tubes and boats for each catalyst, did not yield improved results (not shown).
Gettering may be useful to reduce the concentration of metallic impurities. Ni and Cu are both extremely diffusive in Si, and in high aspect ratio structures such as wires Au should be able to readily be gettered also. This could be achieved, for example, by performing an extended and controlled cool down in the growth furnace after wire growth, or perhaps by post-growth, post-catalyst-removal thermal oxidation of the wires, followed by an oxide etch. It may be possible for an emitter diffusion step to function also as a metal gettering step.
It will also be important, in the pursuit of high efficiency, to choose the doping type of the wire core on the basis of whether p- or n-type material is more tolerant to impurities of the VLS catalyst metal. P-type Si is apparently more tolerant of Cu and Ni impurities than is n-type. [109] However, the device described above was made with an n-type core.
The reason for this is that historically our as-grown wires have been n-type. [55] Recent experiments with more care taken to reduce metal cross-contamination suggests that this n-type doping might be due to Au impurities, and therefore radial pn junction wires with p-type cores and n-type emitters should be revisited.
Finally, no attempt has been made in the above to passivate the surfaces of the wires, and thus the surfaces are likely strong sources of recombination. However, as discussed in Ch. 2, in the radial pn junction geometry the wire cores are shielded from the external surfaces, and it is unlikely that surface recombination alone can be blamed for the relatively poor performance of our devices to date.
Our group has also performed liquid electrolyte PV measurements on Au-catalyzed, VLS-grown Si wire array samples, [120] andVocs of up to∼400 mV have been recorded in this setup. Results with Ni- and Cu-catalyzed VLS-grown Si wire arrays tested in the same setup have to date performed worse than Au-catalyzed samples, surprisingly, but again this could simply be due to unintended Au contamination of these samples. The latter results could also be due to shunting by a surface phase, as no attempt to remove the surface Si was made on the Ni- and Cu-catalyzed samples.