Device Fabrication and Photovoltaic Measurements of Wire Arrays
5.2 Fabrication of a Device Using Grown Wires
5.2.1 Catalyst Removal
After a wire array was grown by the method described in the previous chapter (and repro- duced in Appendix B), the first step towards making a device involved removing the metal
catalyst particle at the tip as well as the near-surface of the wires. For gold the tip was removed the following way: [121]
1. 10:1 solution of DI water : 48% HF for 30 s to remove surface oxide on the Si.
2. 9:1 solution of TFA etchant (Transene): 38% HCl for 20 mins.
3. 10:1 solution of DI water : 38% HCl for 10 s to rinse.
4. Rinse in DI water, dry with N2.
For Cu and Ni the following procedure was used:
1. Buffered HF (Transene) for 30 s.
2. RCA 2 clean (6:1:1 H2O:H2O2:HCl at 70◦C) for 10 mins. [83]
3. Buffered HF (Transene) for 30 s.
4. Rinse in DI water, dry with N2.
In some cases the RCA 2 cleaning step damaged the wire array, apparently by the physical impact of bubble formation on the wire surfaces and/or collisions between bubbles and wires. This was only noticed once, on an array whose wires were1.5μm, and so may not be a problem for larger-diameter wires.
The Si at the near-surface was then removed by immersion of the sample in 60 wt.%
KOH at 30◦C for 30 s. On a planar SOI control sample, with a Si(100) device layer (which is etched slightly less rapidly by KOH than is Si(110) [122]), this was found to remove 23 nm of Si per min. Seidel et al. give the etch rate under these conditions as 18 nm/min for Si(100), and 27 nm/min for Si(110). [122] Prior to doping, we ensured that the pattern oxide is fully removed (from the front side only) to ensure that the wire emitters are all connected. This was done by floating the sample, face down, on a drop of buffered HF (Transene) for about 4 mins.
5.2.2 Doping: Radial pn Junction Formation
The front side of the arrays were then doped n-type by stacking parallel to SiP2O7 diffusion wafers (PH-950, Saint-Gobain Ceramics), introducing to a tube furnace at 750◦C, ramping
100
up to 800 ◦C (over about 5 mins), holding at 800 ◦C for 40 mins, and then ramping back down, all under UHP N2at 5 lpm. The front surface was then exposed to buffered HF for 2 mins. This constitutes the n-type diffusion step. This approach, using post-growth dopant diffusion from source wafers, was taken simply for convenience, and future efforts in our group will look at the use of dopant gases during wire growth.
The samples were then re-introduced to the tube furnace, this time without the SiP2O7 diffusion wafers, at 750 ◦C under house N2 bubbled through near boiling H2O, ramped to 855◦C (over about 16 mins), and held at 855◦C for 20 mins, in order to create a high-quality surface oxide to prevent out-diffusion of the dopant atoms. The gas was then changed to dry house N2, and the temperature ramped up to 1100 ◦C and held at this temperature for up to 23 hours in order to “drive in” the dopant atoms. Temperature was then ramped back down to room temperature, and the samples were not removed from the center of the furnace until the temperature there had at least dropped below 750 ◦C. The front surface was then exposed to buffered HF for long enough that the oxide was removed (determined by the time it took to change a planar control from hyrdophilic to hydrophobic). This constitutes the n-type drive step.
The front surface of the samples were then doped p-type by stacking parallel to BN diffusion wafers (BN-975, Saint-Gobain Ceramics), introducing to a tube furnace at 750◦C, ramping up to 950 ◦C, holding at 950 ◦C for 40 mins, and then ramping back down, all under UHP N2 at 5 lpm. The front surface was then exposed to buffered HF for 2 mins.
This was followed by a low temperature oxidation at 750 ◦C for 20 mins, under O2 at 5 lpm. The front surface was again exposed to buffered HF for long enough that the oxide was removed (determined by the time it took to change a planar control from hyrdophilic to hydrophobic). This constitutes the p-type emitter diffusion step.
This procedure was developed to target a doping level of∼1017dopants/cm3in the wire cores, and a sheet resistance of 50 - 100Ωcm in the emitter [123] (where the optimal emitter dose was determined empirically - diffusions at 900 ◦C or 1000 ◦C were found to reduce planar cell performance relative to a diffusions at 950 ◦C), and involved a combination of modeling using a spreadsheet tool developed by M. D. Kelzenberg, based on standard diffusion models as explained for example in [124] and on empirical data from [125] and [126], as well as 4 point probe resistivity measurements of planar control samples and well- established relationships between Si resistivity and dopant density. [50]
An SOI planar control doped by the same procedure as outlined above was sent to Solecon for spreading resistance depth profiling in order to assess the effectiveness of this procedure in attaining the doping profile we wanted. The results are shown in Fig. 5.1. We indeed see an n-type doping level of ≈1017 cm3 throughout the base, and a highly doped p-type emitter, with surface concentration near the bulk solubility of B in Si at the emitter diffusion temperature, extending several hundred nm into the Si.
5.2.3 Metallization
Finally, the sample edges were cleaved off to prevent macroscopic shunting, oxide was re- moved from the entirety of the samples with buffered HF (Transene), and contact was made to the back surface by immediately rubbing Ga/In onto the back of the sample and the sam- ple then bonded with Ag paste (SPI Supplies) to a piece of stainless steel to which electrical contact could be made with a probe tip. Contact was made to the front surface with a spot of Ga/In and an electrical probe tip. This led to the cell structure as depicted in Fig.
5.2. This method of contacting was used for convenience and was shown on homogeneously doped planar wafer samples to produce ohmic contacts of low resistivity (not shown).