Figure 7.5. SEM image of patterned sol gel. Left: Before annealing, Right: After annealing at 1000◦C in H2 and SiCl4 for 20 min
from the exposed Si, as well as the temperature/chemical stability of the sol-gel pattern, motivated continued investigation of this soft-lithography technique to pattern VLS growth substrates.
Si Back contact Reference
Electrode Cu Counter Electrode
-0.8 -0.6 -0.4 -0.2 0
Potential (V vs. Ag/AgCl)
-50 -40 -30 -20 -10 0
Current (mA2)
Figure 7.6. Left: Schematic of Cu electrodeposition cell. Right: InitialI−E data for Cu electrodeposition on a patterned Si substrate. Potentiostatic deposition was subsequently carried out at -0.4V vs Ag/AgCl.
Experimental procedure
Electrodeposition was carried out using a pressed cell where the substrate was sand- wiched between a glass cell and a stainless steel back contact using a PTFE O-ring (Fig.
7.6). A high purity (6N) Cu mesh or rod served as the counter electrode, and Ag/AgCl was used as the reference electrode. Electrodeposition was carried out potentiostatically at -0.4 to -0.6 V vs. Ag/AgCl. The potential for deposition was chosen to be halfway between the onset of deposition and the mass transport/ solution resistance limited current density (Fig 7.6).
Cu plating solutions
Several different plating solutions have been investigated as Cu sources for the VLS catalyst. The standard plating solutions available commercially consist of CuSO4 salts in aqueous H2SO4 with additional additives to improve adhesion and control grain size.[110]
A high-purity control solution (0.1 M CuSO4(5N) and ultrapure 1.8M H2SO4) was used, as well as plating solutions from Transene (Acidic Cu) and Clean Earth Solutions (Cu Primer).
Inductively coupled plasma mass-spectrometry (ICP-MS) was used to verify the composition of the solutions, and while the results were only semi-quantitative, they indicated that the commercial plating solutions did not contain high concentrations of metals that are known to cause deep-level traps in Si.
One of the major challenges in the electrodeposition process is maintaining adhesion
Figure 7.7. SEM images of electrodeposited Cu on a 10 x 20µm patterned SiO2/Si substrate before (left) and after (right) annealing at 1000◦C for 20 min
between the Si wafer and the Cu disk. When removing the sample from The surface tension at the liquid-air interface often dislodges the Cu disks from the substrate. Using substrates with thicker (1.5–2µm) SiO2 layers and optimizing the amount of Cu deposited inside the oxide wells minimized the lift-off of Cu after electrodeposition. Figure 7.7 shows an SEM of patterned, electrodeposited Cu before and after annealing at 1000◦C.
7.5.1 Controlling wire diameter
Simulations of the performance of Si MW array photovoltaics predict that for Si with minority carrier diffusion lengths>10µm, wires with diameters of 10µm should be able to achieve 10% efficiency under AM 1.5G illumination.[102] While this model does not account for all of the optical properties of the wire arrays, it motivates the investigation of wires with larger diameters than have been previously been studied. Electrodeposition provides the ability to control the amount of the Cu VLS catalyst without worrying about thickness limitations due to lift-off for lithographically defined metal films, allowing the diameter of wires to be increased more than was possible using evaporation of the catalyst. Prior work in the Lewis group focused on increasing the density and diameter of VLS wire arrays by changing the photolithographic pattern and electrodepositing Au as the VLS catalyst.[111]
Here, a similar approach was taken to precisely control the amount of Cu electrodeposited, and eventually correlate this with the diameter of the VLS grown microwire arrays.
Figure 7.8 shows the relationship between Cu thickness (measured by cross-sectional SEM) and the charge density passed (based on the exposed Si area). This empirical rela-
1 2 3 4 5 6
Charge Density (area=exposed Si, C cm )
200 400 600 800 1000 1200 1400 1600
Cu thickness (nm)
3x7 μm hex 10x20 μm hex
-3
Figure 7.8. Left: Comparison of electrodeposited Cu thickness with charge density passed during electrode- position. The data shown is for hexagonally packed patterns at different diameters and ptiches. Right:
SEMs of electrodeposited Cu of different thicknesses and geometries
tionship was developed as a useful tool for predicting Cu thickness over a wide range of pat- tern geometries, since the measured thicknesses systematically varied from the thicknesses predicted by a simple faradaic analysis of the charge required for electrodeposition.[111]
7.5.2 Electrodepositing on Si patterned with sol-gel
Cu electrodeposition was also carried out on substrates patterned with sol-gel. The thin sol-gel layer made it difficult to maintain Cu adhesion to the substrate, as shown in the top images of Fig. 7.9. However, by using plating solutions with brightening and adhesion additives, it was possible to maintain adhesion over large areas (bottom of Fig. 7.9). Work is underway to increase the thickness of the sol-gel layer to improve adhesion of the Cu disks.
7.5.3 VLS wire growth
Arrays of VLS Si microwires were grown using the procedure discussed in Chapter 2. Af- ter electrodeposition, substrates were gently rinsed with 18 MΩ-cm water to remove any unreduced metal salts and then loaded into the growth reactor. Figure 7.10 shows SEM images of VLS Si MW arrays grown on sol-gel patterned substrates using electrodeposited Cu as the VLS catalyst (A and B show as grown wires, and C shows the wires after catalyst removal).
Figure 7.9. Top: SEM images of electrodeposited Cu with poor adhesion to the sol-gel patterned substrate.
Bottom: SEM and optical images of electrodeposited Cu in patterned sol-gel
After growth, the Cu VLS catalyst was removed using two RCA2 cleans and then the wires were characterized using by making single-wire solid-state devices and using photo- electrochemistry. The sol-gel used to define the wire pattern etches much more quickly than a thermally grown SiO2layer, and was completely removed during the standard clean- ing procedure. To prevent shunting between the degenerately doped base and electrolyte for these samples during photoelectrochemical characterization, the wires were “booted”
using the standard thermal oxidation and partial PDMS infill procedure. (In a manufac- turing setting where the final device is removed from the substrate, this step would not be necessary.)
Figure 7.10. VLS wires grown from electrodeposited Cu patterned with micro-imprint lithography. A: Large area, B: Single wire, C: After Cu removal