3.8 Temperature Sensitivity
3.8.3 Impact on Floating-Gate Devices
0.4 0.6 0.8 1 10−14
10−12 10−10 10−8
gate−source voltage: V
gs
source current: Is (log scale)
T=275 T=300 T=325 T=350 T=375 T=400
1 2 3 4
0.5 1 1.5 2
x 10−5
gate−source voltage: V
gs
source current: Is
T=275 T=300 T=325 T=350 T=375 T=400
Figure 3.40: Physical simulations in Atlas show temperature dependence of transistor current. Below threshold, current increases with temperature. Above threshold, the opposite relationship holds, such that current decreases with temperature. The point where the relationship inverts is called the temperature compensation point (TCP). The same data is plotted on a log scale (left) and linear scale (right). Left: Below threshold. The upward shift (on the log scale) for successively higher temperatures can be characterized by the term e−φ0/kT. The decreasing slope with temperature can be explained by the term eqVgskT . Note that the simulated transistor was not saturated, so the temperature dependence of the Early effect term would decrease the current as a function of temperature by about 0.5% over the temperature range shown. Right: Above threshold.
plots. Note that the slopes decrease with temperature. The derived eqn. 3.20 is consistent with physical simulations in Atlas. Both sources indicate that the general trend in subthreshold is for current to increase with temperature, but the rate of increase lessens for largeVgs.
In summary, in weak inversion, increasing temperature generates electron-hole pairs in the chan- nel. The increased number of carriers results in an increased subthreshold current. In moderate inversion, the opposite temperature coefficients of mobility and voltage threshold shift counter one another and result in small changes in channel current as a function of temperature. In strong inversion, decreasing mobility with temperature results in an overall decrease in current.
−0.52 0 0.5 1 1.5 2 2.5 3 2.5
3 3.5 4 4.5 5
cgg (fF)
vgs (V)
Vds = 3.0 Vdd = 3.0 Vth = 0.6
NFET gate capacitance
Figure 3.41: NFET gate capacitance as a function of the gate–source voltage Vgs, from an EKV model simulation. As described in the text, the capacitance decreases as the channel becomes more strongly depleted due to increasing gate voltage in subthreshold. When the device reaches threshold, the channel inverts and gate capacitance returns to its maximum, proportional toox·A/tox, where Ais the area of the device.
is turned off, the capacitance per unit area between the gate and channel is simply Cox =ox/tox, whereoxis the dielectric constant of SiO2andtoxis the thickness of the oxide between the gate and channel. AsVg increases, majority carriers are pushed away and the surface of the channel becomes depleted. This can be represented as a weak downward band bending. Recall that the surface potential, φs, corresponds to the energy levelq·φs whereEC intersects the silicon-oxide interface.
Whenqφ˙s is between EC and Ei, the channel is depleted. Since no carriers exist in the depletion region, the effective dielectric thickness is now equal totox+Wdep, where Wdep is the thickness of the depletion region, and the capacitance per unit area now equals Cox+Cdep = tox
ox + Wsi
dep. As the gate voltage increases, the bands bend more. Threshold voltage is the gate voltage at which the conduction bandECbends enough to intersectEF at the silicon-oxide interface (that is,q·φs=EF) as shown in in fig. 3.42. In other words, threshold is the point at which the channel inverts. The inverted channel contains plentiful charge carriers and the dielectric thickness is againtox. Since the effective dielectric thickness in subthreshold is greater than either when the transistor is fully off or when it is fully inverted, the capacitance is lowest just below threshold.
Above threshold, the MOS capacitance depends primarily ontoxandox, neither of which changes much with temperature. The temperature coefficient of the MOS capacitance is very small, on the order of 20ppm/◦C [67] or 50ppm/◦C [4]. In fact, the modern BSIM3V3.3 model and earlier versions of BSIM3V3 do not even include a parameter to simulate this thermal coefficient directly, and indeed simulations based on this model show no temperature dependence of the capacitance of a MOSFET.
For a floating gate holding a constant charge and coupled only to above-threshold transistors, we can expect the effect of temperature on the voltage to be very small. This effect is certainly smaller
EC
EV Ei EF
p-type silicongate oxide
EC
EV Ei EF
EF at higher temperature
EF at lower temperature
Figure 3.42: Left: The band diagram of an MIS diode. A positive bias applied on the gate causes the bands to bend downwards. When the conduction bandEcreaches the Fermi levelEF, as shown here, the device is at threshold. The potential difference between the intrinsic and Fermi levels is defined byqφb ≡Ei−EF. The level of the conduction bandEC at the silicon-oxide interface defines the surface potential,φs. Right: As temperature increases, the intrinsic carrier concentration increases.
This causes the Fermi levelEF to shift closer toEi. The amount of band-bending necessary forEC
to reachEF is thus reduced, which corresponds to a decreased threshold voltage for the device.
than the effects of mobility and threshold voltage that affect the operations of floating-gate and non-floating-gate circuits identically.
In subthreshold, on the other hand, a clear temperature dependence exists because the depletion layer thicknessWdep changes with temperature. Wdep is equal to [73]:
Wdep=
2sφs
qNa
The permittivity of silicon s and the charge of an electron q are constants. Na is the impurity concentration, set at fabrication. Only the surface potentialφs is dependent on temperature. Cal- culating the value ofφs is not straightforward. However, we can approach the computation from another angle. As shown in fig. 3.42, the Fermi levelEF shifts closer toEi with temperature, equiv- alently expressed as a decrease inq·φb. Since threshold voltage is the voltage necessary to bendEC
enough to intersectEF at the oxide-silcon interface, decreasingφb directly decreases the threshold voltage:
Vth=VF B+ 2φb+ other terms
0 20 40 60 80 100 120 2.46
2.465 2.47 2.475 2.48 2.485 2.49 2.495
temperature (C)
total gate capacitnace cgg (fF)
Figure 3.43: Change in gate capacitance for ann-channel transistor, as estimated from the EKV model (fig.3.41) and equations for voltage threshold shift (eqn. 3.21).
whereVF B is the flat-band voltage. The temperature depencence ofφb is described by:
φb = kT q ·ln
Na
ni
where
ni = 2· 2πkT
h2 32
·(m∗nm∗p)34 ·e−Eg/2kT
and thus
φb = kT q ·
Eg
2kT −3 2ln
2πkT h2
+ ln
Na
2 ·(m∗nm∗p)−34
(3.21)
wherehis Planck’s constant,m∗n and m∗p are the effective masses of electrons and holes, andEg is the bandgap. In short,φb will vary with temperature asT ·ln(T). A shift in threshold voltage is equivalent to the same magnitude shift parallel to the x-axis of fig. 3.41. Using eqn. 3.21 to compute the shift in threshold voltage and applying the resulting change in gate capacitance from the data in fig. 3.41, we estimate that for this NFET the gate capacitance will change at 2.489 fF per 100◦C, or 1.18% per 100◦C. The results are shown in fig. 3.43. This is an approximation and the exact change in capacitance may vary with the biasing of the device.
−50 0 50 100 1.05
1.1 1.15 1.2 1.25 1.3
Temperature (C)
Vph
−50 0 50 100
3.2 3.25 3.3 3.35 3.4
Temperature (C)
Vout
Figure 3.44: Cadence simulations of the effect of temperature on photoreceptor output, assuming constantVf g. The general trend is that the photoreceptor output voltage increases by 1.835 mV/◦C forVph and 1.113 mV/◦C for Vout. Top left: Unbuffered photoreceptor output (Vph) as a function of photocurrent for several temperatures. Top right: Photoreceptor output buffered by a source- follower (Vout) as a function of photocurrent for several temperatures. Bottom left: For a single photocurrent, unbuffered photoreceptor output as a function of temperature. Bottom right: For a single photocurrent, buffered photoreceptor output as a function of temperature.