3.5 Sample-and-Hold Circuit
3.5.2 S/H Measured Data
charge as N7. Instead, I widened the NFET cascode transistors by a factor of three to equalize the expected feedthrough due to this capacitive gate-to-drain coupling. This worked well in simulation.
Note however that if the mismatch between the cascode transistors is greater than the inherent difference in operation between NFETs and PFETs, then mismatch could be a greater contributor to the size of the pedestal. A balance must be struck between these two factors. Simulation was used again to verify that the impact of mismatch in this regard was minor.
Consider the effects of mismatch elsewhere in the S/H circuit. Because of the feedback configu- ration, mismatch resulting in varying values ofVholdwill have some effect on the range of the circuit but is generally a minor concern. Mismatch in the input pair P2 and P3 could manifest itself as an offset between Vin and Vout, however, and thus could be worrysome. The input pair (P2 and P3) and the current mirror (N8 and N9) were laid out with common-centroid and photolithographic invariance1[5]. Their sizing was chosen to facilitate this layout.
The NMOS capacitor Ncapneeds to be sized to reduce charge leakage over the hold time period.
A 6µm×6µmNMOS capacitor shows acceptable leakage in simulation for temperatures up to about 50◦C.
2 3 4 5 2.5
3 3.5 4
sample hold
2.3 2.4 2.5 2.6 2.7
2.3 2.35 2.4 2.45 2.5 2.55 2.6 2.65 2.7
Sampled Held fit to samp fit to held
4.3 4.35 4.4 4.45
4.3 4.35 4.4 4.45
Sampled Held fit to samp fit to held
Figure 3.29: Measured data for a single sample and hold circuit. Left: Entire operating range.
Center: Zoomed in near 2.5V. Right: Zoomed in near 4.4V. The input Vrst is swept (x-axis). The blue lines indicate the output of the sample-and-hold circuit in sample mode. The red line indicates the output after the transition to hold mode. As can be seen from this figure, the functional range of the circuit is from 2.45V to 4.42V.
is a function of the current in P11, since Vhold will move to whatever value is necessary for the currents in P10 and P11 to be equal. In the data shown, the current in P10 was large enough that forVin<2.7,Vholddropped below the threshold voltage of Ncap. The capacitance of this MOSCAP thus decreased. For a constant amount of charge injected onto the capacitor, the resulting voltage jump (the pedestal) was thus larger. The magnitude of the pedestal for Vin < 2.7V could be decreased by setting a lower bias current through P10, or at design time by making P10 wider.
For 2.7< Vin<3.8, the circuit operates as previously described. Transistor N7 is in saturation and above threshold.
AsVinincreases above 3.8V, P3 goes into subthreshold. The absolute amount of charge flowing through the channels of P5 and N7 decreases significantly. The pedestal is minimal simply because there is minimal charge that might be injected in the channels of these two transistors. In this region, most of the injected charge must be coming from gate-drain capacitive coupling asVncasand Vpcasswing toVgndandVdd. That the pedestal is closest to zero forVncas≈1.2V whenVpcas= 2.2V suggests that at these voltages, the capacitive coupling is equal for P5 and N7.
The value ofVncas also affects the size of the pedestal, as shown in fig. 3.30. At the transition from sample to hold mode, the gate of N7 drops fromVncas to Vgnd to turn off N7. This voltage swing couples capacitively through the gate-drain capacitance of N7 ontoVhold, injecting negative charge onto the hold capacitor. Since for higher values ofVncas this swing is larger, more negative charge is injected. For values ofVncas below 0.7V, the cascode NFETs N6 and N7 turn off and the amplifier does not work (data not shown).
Similarily, the value of Vpcas affects the size of the pedestal as shown in fig. 3.31. As Vpcas is
2 2.5 3 3.5 4 4.5
−50
−40
−30
−20
−10 0
Sample−and−Hold input Vin (V)
pedestal mean (mV)
ncas=2.000 ncas=1.755 ncas=1.500 ncas=1.200 ncas=1.000 ncas=0.800
Figure 3.30: Effect of sweepingVncas on the size of the pedestal withVpcas= 2.2V.
2 3 4 5
−15
−10
−5 0 5
Sample−and−Hold input (V)
pedestal mean (mV)
pcas=0.000 pcas=0.500 pcas=0.800 pcas=1.000 pcas=1.250 pcas=2.000
Figure 3.31: Effect of sweeping Vpcas on the size of the pedestal withVncas= 1.0V.
VgradX>VthH VgradX<VthL
VgradY>VthH VgradY<VthL
SAL VgradX
VgradY
nSALX
nSALY
VthH
Memory Cell
Memory Cell
VthL
− +
Vgrad
Vgrad > VthH
− + Vgrad
Vgrad < VthL
Figure 3.32: Left: The saliency circuit. If the input gradient valueVgradX (or VgradY) exceeds the boundaries of the programmed thresholdsVthLandVthH, the intermediate saliency valuenSALX(or nSALY) will be zero. If bothnSALXandnSALY are zero, thenSALwill be high. Thus, the circuit will be deemed salient only if both the X and Y gradients exceed the thresholds. Right: Subcircuits to compare the gradient values to preset thresholds. The Memory Cells [30] are programmed by tunneling and injection to store the thresholds.
increased, it must move a smaller distance to reachVdd during the transition to hold mode. Less positive charge is thus injected ontoVhold due to capacitive coupling between the gate and drain of P5, and the pedestal becomes more negative.