Equations (3.1), (3.2), and (3.19) describe the peak output voltage drops during the three intervals of the buck converter transient response. These three equations are reproduced here for convenience.
dI 1 M 2
AV =~VI +~V,
=
ESL-o +ESR.Mn + __ 0 _t i " I ' , - dt 2 C ----"-dl
o dt
(3.25)
In
'[I_
VO ]f, .Co Vill (3.26)
Vo . I
V 0 1 k·I
~
v- =
ill + - . __ 0 •f .
C . ESR 2) 2 . Co' k . f, 2 Vo \ 0 (3.3)
Vin
Obviously, minimizing all three voltage drops yields the best overall transient response.
However, the question is how to get the best overall transient response in the smallest volume, with the lowest cost, and with the highest overall efficiency.
From (3.25) it is clear that ~ Vol depends only on the ESR and the ESL of the output capacitors, and is unaffected by any other circuit parameters like the switching frequency or the control loop bandwidth. Thus, the only way to reduce ~ Vol is to choose high quality capacitors and place a number of them in parallel. Here again the issue of electrolytic capacitors versus ceramic chip capacitors arises. If ceramic chip capacitors are used, ~ Vol will be very small because there will be a large number of low ESR and
34
low ESL capacitors at the output. However, meeting transient specs during II may not insure adequate performance during hand l; as well. As a result, the number and type of capacitors that will need to be placed at the output will also depend on what happens during the intervals hand h On the other hand, if electrolytic capacitors are to be used, because of their rather high ESR and ESL a number of them will have to be placed in parallel in order to maintain L'l Vol small. In this case, the ESR and the ESL determine how many capacitors will have to be used. Typically, however, the amount of output capacitance dictated by L'l Vol will far exceed the capacitance requirements imposed by the intervals 12 and
h
The peak voltage drop during the intervals hand l; is given by equations (3.26) and (3.27), respectively. These equations show that good transient response requires either a large output capacitor or a high switching frequency. The optimal solution finds the right balance between VRM size (dictated by the number and the size of the output capacitors) and efficiency (dictated by the switching frequency). For example, from Fig. 3.7 we can see that the total output voltage drop of 150m V during hand l; can be achieved with 270)lF of output capacitance at a switching frequency of 500kHz. However, meeting the 150m V specification with 270)lF of capacitance requires k~O.2 (see Fig. 3.7).
It should by now be clear that there are two design paths that can be taken. One possibility is to keep the switching frequency low and rely on the output capacitors to keep the output voltage within specs. There are several problems with this approach.
First, bulky electrolytic capacitors required at the output dramatically increase the volume of the module and prevent its use in laptop applications. For now, however, such solutions are still finding their place in the desktop market (where the space is not as
limited) due their low cost. Second, this approach suffers from the lack of scalability.
Namely, the trend in the processor industry has been to demand higher core currents with higher slew rates to be provided by the VRM for every new generation of processors. As a result, relying extensively on the output capacitors to do all the work will quickly become a totally unacceptable solution even in the desktop market because of size issues.
Therefore, the low frequency, large output capacitor approach is at best a short-term solution and will not be considered here.
The other VRM design path is based on minimizing the role of the output capacitors in keeping the output voltage within specs. Instead, it is desirable to have a fast, high bandwidth control loop do the bulk of the work in keeping the output voltage within the prescribed limits after a fast load current transient. This is achieved by opting to operate the converter at a higher than usual switching frequency. The high frequency, low output capacitance approach advocated in the rest of this thesis produces a scalable, high power density, low volume solution that will be able to efficiently meet future processor power demands.
3.3.1 Merits of the High Switching Frequency
The obvious benefit of a higher switching frequency is the reduction of the physical size of the buck inductor. A smaller inductor helps to reduce the size of the converter. In addition, having a smaller inductor allows the inductor current to be changed faster. This allows the circuit to reach a new steady state sooner. Consequently, transient specs can be met with less output capacitance, which further reduces size of the converter.
Another benefit of high frequency operation is that it shortens the maximum response delay time (interval h). Consequently, a high switching frequency results in a smaller
36
peak voltage drop during
h
Again, this helps In reducing the SIze of the output capacitor, and thus, the size of the whole module.Operating at a high switching frequency makes it possible for the feedback loop to have a high bandwidth. The benefits of a high bandwidth control loop and a small inductor, both results of operating at a high switching frequency, are felt during the interval h where both help to minimize i1V5 (see (3.14) and (3.27».
In short, a higher switching frequency allows the designer to reduce the size of both the buck inductor and the output capacitors and increase the bandwidth of the control loop. As a result, the overall size of the VRM is significantly reduced. On the down side, however, operating at a high switching frequency will lower the efficiency of the converter and require advanced packaging techniques.