Phased Array Architectures

Chapter 2 Fundamentals of Single-Path and Multi-Path Receiver 4

2.2 Phased Array Systems

2.2.5 Phased Array Architectures

As a single-path receiver, the phased array receiver can be realized using various down conversion schemes such as superheterodyne, direct conversion, wide-band IF, low-IF, etc., involving similar trade-offs in signal-path design. Phased array receiver can also be classified by where the delay compensation is performed, namely, passive RF, active RF, IF, analog baseband, digital domain, or LO path.

Figure 2.16 shows the passive RF phase shifting architecture. Passive phase shifters or time delay elements directly follow the antenna elements. Their outputs, the phase or delay compensated signals, are summed via a combining network fed into a single LNA input. The true time domain compensation, resulting in broadband frequency response, can only be achieved by using time delay elements before the first frequency translation. Such time delay can be realized using transmission lines whose effective length can be adjusted electronically [28]. A single-path receiver can be readily employed in this architecture. Since the signal combining process enhances the signal level and tremendously attenuates the interference, the noise and linearity requirements of the LNA are greatly relaxed, allowing them to trade off with other system performance. The main drawback of this architecture is that the loss of the phase shifters and combining network directly degrades the receiver sensitivity, and so they are limited to waveguide type in practical implementation, which are bulky, heavy, and expensive, prohibiting wide-spread usage. Another limitation of passive phase shifting is the lack of amplitude control.

Figure 2.17 illustrates the active RF phase shifting architecture. In this architecture, the phase shifters or delay elements are introduced after the LNAs. The multiple LNAs increase the system power consumption. However, thanks to the LNA gain, the phase shifters do not need to be optimized for low loss. The amplitude control can also be realized using RF VGA. The space processing at RF relaxes the DR requirements of the mixer and the subsequent blocks. The design challenge is to create compact, linear, wideband and relatively low-loss RF phase shifters, which are difficult to realize in integrated implementation.

The IF phase shifting architecture is shown in Figure 2.18. After the LO signals with identical phases mix with the RF signals, only carrier phases can be compensated

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Figure 2.17: Active RF phase shifting architecture

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Figure 2.16: Passive RF phase shifting architecture

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Figure 2.18: IF or baseband phase shifting architecture

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Digital Signal Processing

Figure 2.19 Digital phase shifting architecture

correctly. The time delay compensation at IF will give rise to an unbalanced phase in each path owing to the mixed LO signals. Hence the IF phase shifting is only suited for narrow band modulation. When the phase shifting stage moves towards the back- end of the receiver, fewer unshared components increase the overall system noise and power consumption. Moreover, the unshared blocks before the signal combining experience the same SINR so that they need to provide the same DR as those in single-path receiver, implying an additional increase in power. Compared to the RF phase shifter, the IF phase shifter exhibits lower loss and lower power consumption due to the lower operation frequency. However, the dimensions of the passive devices, i.e., the inductors and capacitors, used in phase shifters are generally reversely proportional to operation frequency. Therefore, the IF phase shifting consumes more valuable silicon area than the RF phase shifting. The same tradeoff applies to analog baseband phase shifting.

Taking advantage of the large amount of transistors provided by CMOS technology, the amplitude and phase control can be performed in digital domain as shown in Figure 2.19, referred to as digital phase shifting architecture. Using a digital signal processor (DSP), the space processing can be performed with various algorithms, suggesting the most versatile topology. However, each block in the single- path receiver has to be multiplied in this array implementation, including the power hungry ADC, which might make it exceed the power budget of a portable device and

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Figure 2.20: LO phase shifting architecture

the most noisy implementation among all the architectures. Another serious design challenge is the high-speed high-throughput data I/O of the DSP, which is currently a bottleneck to the achievable bandwidth of this configuration.

An alternative approach for an integrated implementation of such a system is to perform the phase shifting in the LO path in this so called LO phase shifting architecture as shown in Figure 2.20. The possible amplitude control can be realized by employing the variable amplifiers at the RF or IF stages. If different downconversion mixers are driven with LO signals of different phases, we can achieve the phase shifting at the LO and approximate the delay elements over a limited bandwidth. This architecture is advantageous in that amplitude noise and mismatches at the LO path do not deteriorate the receiver sensitivity and spatial selectivity directly. Moreover, this architecture is particularly attractive for silicon- based integrated systems due to the possibility of accurate multiple phase generation and distribution [35].