Chapter 1 Introduction
2.2 Basics of Electrical Links
2.2.3 Receiver
Figure 2.23: Different high-frequency boosting configurations.
The main advantage of the continuous time equalization is that it mainly employs passive components and therefore has minimum power overhead. Figure 2.23 illustrates some circuit configurations employing inductors to perform high frequency boost. Detail analysis of these designs can be found in [38]. Passive continuous-time equalization is mainly employed in the receiver side, as will be explained in the next section, however transmitter equalization could be advantageous compared to receiver continuous equalization due to better noise performance. This is due to the fact that receiver high frequency peaking also amplifies high frequency noise where the signal strength is at its lowest, and hence degrades the overall SNR. The main drawback of this technique is the use of inductors, which inherently require large area. In the next chapter we will introduce a design that rectifies this problem.
Figure 2.24: A typical electrical receiver block diagram.
Another important aspect of receiver design is the capability to compensate for the channel dispersion. We previously discussed the options for equalization at the transmitter side. However, as the data rate increases while the channel characteristics remain almost the same, the transmitter equalization becomes less than adequate for the excessive channel loss. Therefore designers have employed receiver equalization in conjunction with transmitter equalization to make high data rates possible over bandwidth limited channels. In the next section we will discuss different receiver equalization techniques.
2.2.3.1 Receiver Equalization
Receiver equalization is a powerful tool to compensate for the frequency dependent loss of the electrical channels. In this section we will introduce different techniques that are commonly employed by link designers to implement equalization at the receiver.
Decision Feedback Equalization. A common approach to remove ISI and enhance SNR is to employ decision feedback equalization (DFE). This technique helps to compensate for post-cursor ISI arising from the spread of a single pulse over time. The high level block diagram of a typical DFE is shown in Figure 2.25, [39]. The ISI from previous bits is compensated by adjusting the DFE taps: w1, ..., wn . The delay elements taking on values of unit bit-times can be implemented using latches and flip-flops. In the DFE, weighted
Figure 2.25: Simplified block diagram of a decision feedback equalizer.
versions of previous samples are added or subtracted to the main sample by a summer at the front-end.
The main problem in the design of a DFE is to meet the timing requirement for the first tap feedback loop. The constraint imposed by this critical signal path is that the sum of the slicer delay, the settling time of the summer, and the setup time of the latch needs to be less than one bit-time. Satisfying such a timing requirement becomes a difficult problem at increasingly high data rates. The problem can be mitigated by the application of speculative techniques, known also as loop-unrolling [40]. A block diagram of speculative DFE and the new critical path associated with this approach is shown in Figure 2.26. Basically, in this approach the outcomes for both possible values (one and zero) of the previous bit are fully resolved to digital levels. A multiplexer then chooses the correct value based on the resolved previous bit. Therefore, two latches are required to restore the digital levels. This technique can be further extended to the second equalization tap by resolving the incoming bit for four different cases possible for the previous two bits. Applying this technique to more taps, increases the complexity of the system exponentially. As a result, it is common to only apply it to the first tap. Recently, in order to enable data rates in excess of 25Gb/s, 2-tap [41] and 3-tap [42] loop-unrolling has been also employed.
Figure 2.26: Loop-unrolling of the first tap of the DFE to remove the critical feedback loop.
Feed-Forward Equalization (FFE). Over the years one of the simplest and mostly used equalization techniques has been linear feed forward equalization (FFE). This technique usually involves the use of a linear transversal finite impulse response filter (FIR) as shown in figure 2.27. The FIR consists of adjustable tap coefficients w1, ..., wn and a discrete or continuous unit delay, z−1 between each tap. The amount of delay, τ that each delay cell represents can be as large as the bit-time [43], which is often referred as a symbol spaced equalizer. If τ < Tb the equalizer is called a fractionally spaced equalizer (FSE) [44–46].
With proper selection of the tap gains this type of equalizer can be used to cancel pre- cursor ISI, post-cursor ISI or both. Figure 2.22 illustrates how a weighted delayed version of the received pulse can be employed to remove post-cursor ISI. Similarly they can be used to compensate for pre-cursor ISI. Such a structure is very flexible, capable of handling any pulse response so long as a sufficient number of taps is provided. The choice of the delay cells could be either digital or analog. Digital FIR filtering requires a high-speed data converter. An alternative technique is to use sample and hold circuits as the tap delay line [43]. Another approach is to employ analog delay cells such as passive delay lines [44–46] or inductor-less active delay lines [47]. Passive delay lines employ inductor and variable capacitors to provide adjustability. They also achieve very high data rate. However, large on-chip inductors lead to a large die area. Inductor-less designs can achieve small area but they are limited to low data rates.
Figure 2.27: Feed-forward equalization at the receiver.
Continuous Time Linear Equalization (CTLE). Receiver equalization can also be implemented with a continuous-time amplifier that provides a high frequency boost. Usually the transfer function of these kinds of amplifier are adjustable to accommodate different channels. These amplifiers can be employed at the receiver front-end as the pre-amplifier to not only increase the signal level reaching the slicer, but to partly compensate for the channel loss. An example of such amplifier is shown in Figure 2.28. Here, programmable RC-degeneration in the differential amplifier creates a high-pass filter transfer function which compensates the low-pass channel [48, 49].
Another example of the continuous time linear equalizer is shown in Figure 2.29(a). This passive equalizer acts as a high-pass filter to compensate for the channel loss [49]. However, it introduces loss at low frequency which degrades the SNR at the slicer input. As a result, in most applications it is followed by an amplifier to improve SNR. The linear equalizer shown in Figure 2.29(b) employs a high frequency and a low frequency path to achieve high frequency boost [50].
While the implementation of the continuous-time linear equalizer is a simple and low- area solution, one issue is that the amplifier has to supply gain at frequencies close to the full signal data rate. This gain-bandwidth requirement potentially limits the maximum data
Figure 2.28: Continuous-time receiver equalization using frequency dependent source degeneration.
Figure 2.29: Passive high-pass filter equalizer (a). Dual path continuous-time equalizer (b).
rate, particularly in time-division demultiplexing receivers. In addition, the frequency boost introduced by the CTLE also amplifies the high frequency noise and degrades SNR at the receiver. This is especially problematic at high data rates, as the received signal is weak.