Chapter 1 Introduction
6.1 Wire Characteristics
Figure 6.1: On-chip interconnect length trend.
the chip area. It is desired to minimize the chip area to shorten the length of the wires (this improves performance) and to enhance manufacturing yield, which helps reducing the chip cost. On the other hand, in order to meet power density constraints, the chip size has to be increased. Chip temperature is very important as it affects both reliability and speed of various components on an IC.
Because the increasing complexity of VLSI chips continuously demands more from in- terconnects, a systematic and a realistic study of limitations of the currently used electrical interconnects under scaling is of great importance. In the remainder of this chapter we investigate the characteristics of the on-chip wires and develop simple models to analyze their behavior. Finally we investigate the effect of scaling on on-chip wires and discuss the resulting challenges.
Figure 6.2: On-chip metal stack in different technology nodes, 130nm (a), 65nm (b), and 32nm (c).
and a 32nm technology from 2008, employing nine copper metal layers [152]. Between these three technologies the wires’ cross-sectional areas and spacings have dropped dramatically.
The importance of cross-sectional area and spacing lies in their effects on the wire electrical characteristics, resistance and capacitance. The following sections describe geometric models for resistance and capacitance that are based on cross-sectional area and spacing. We will also discuss wire inductance and why we can ignore its role in the performance modeling.
6.1.1 Resistance
All wires have a finite conductance, representing the ability of the wire to carry a charge flow. Aluminum and copper wires, which have been used in most CMOS processes, have a resistivity of 3.5-4.0µΩ.cm and 2.6µΩ.cm, respectively. Resistance (per unit length) can be approximated by the material resistivity divided by the conductor’s cross-sectional area, but several wire non-idealities affect this model.
Most processes prior to 180nm generation employed aluminum wires. Modern processes use copper to reduce the resistivity and also to obtain better electromigration characteristics.
Figure 6.3: The schematic profile of diffusion barrier layer (a). SEM cross section of the diffusion barrier layer [171] (b).
For copper wires, a thin barrier layer, which has much lower conductivity, is required to prevent copper from diffusing into the surrounding oxide, Figure 6.3. As a result of this diffusion barrier layer and reduced effective cross-sectional area, the resulting resistance of the copper wires decreases. Moreover, the barrier layer may not be deposited evenly, which further degrades the wire conductivity. Another wire non-ideality is the surface scattering effect. When traveling along a wire, electrons inelastically scatter off lattice bonds at the edges of wires due to the surface roughness. As the wire dimensions grow smaller, the mean free path of electrons will reduce, effectively increasing the material resistivity [153].
Using advance fabrication techniques such as atomic layer deposition (ALD) an almost constant thickness barrier layer can be created [147], which results in the wire resistance being equal to
Rwire=αscatter× ρef f ective
(t−δ)(w−2δ), (6.1)
whereαscatteris the resistance degradation factor due to surface scattering,ρis the resistivity of the the thin film copper, δ is the barrier layer thickness,w is the wire width, and t is the wire thickness.
Figure 6.4: A simple capacitance model for on-chip wires.
6.1.2 Capacitance
All wires have capacitance, modeling the ability of the wire to store electrical charge. To accurately model the capacitance of an on-chip wire both bottom-plate and fringing capac- itances have to be taken into account [154]. The fringe capacitance models the field lines emerging from the edge and top of the wire. On-chip wires suffer from large aspect ratio (the ratio between the height and width) which makes the fringing portion of the capacitance significant. Therefore, capacitance is best modeled by four parallel-plate capacitors for the top, bottom, right, and left sides, as shown in Figure 6.4, plus a constant. This extra term lumps all the fringing field terms together and approximates their sum as a constant.
The total wire capacitance can be approximated as [155]
Cwire=0(2M horizt
s + 2vertw
h) +Cf ringe, (6.2)
where horiz and vert represent the horizontal and vertical relative permittivity. This differ- ence occurs in technologies that leverage low-k materials. The top and bottom plates are typically modeled as being grounded as they typically constitute a collection of orthogonally- routed conductors that, averaged over the length of the wire, maintain a constant voltage.
Capacitors to the left and right, on the other hand, have data-dependent effective capaci- tances that can vary: if the left and right neighbors switch in the opposite direction to the wire, the effective sidewall capacitances double, and if they switch with the wire, the effective sidewall capacitances approach zero. We model this multiplication effect by varying the M parameter in Equation 6.2 between 0 and 2; this is known as Miller factor (M). These left and right neighbors are also the worst offenders for noise injection. The fringe term depends only weakly on geometry.
6.1.3 Inductance
Inductance is beginning to be important for accurately modeling on-chip wires. Unlike resistance or capacitance, inductance has no simple closed-form models. For advance CMOS technologies, the wire inductance can be ignored and the wire can be treatedRC with a good accuracy [156, 157]. According to [158], if the length of the wire falls within a certain range, Equation 6.3, the inductance effects are significant. This range depends on the parasitic impedances of the interconnect per unit length as well as the rise time of the signal at the input of the CMOS circuit driving the interconnect.
tr 2√
LC < l < 2 R
rL
C. (6.3)
The upper bound of the range represents the case in which the inductance is not important because of the large transition time of the input signal. On the other hand, the lower bound shows the case where the wire attenuation is so large that the inductance becomes unimportant. Figure 6.5 shows the region in which the wire inductance becomes important for 28nm CMOS technology.