Fig. 4.14. I-V curves as functions of dose and room temperature annealing for transistors from the same InGaAs FinFET wafer as the capacitors of Figs. 10-13, irradiated with gate biases of (a) VG = +1 V and (b) VG = -1V.
CHAPTER V
CONCLUSIONS
In this thesis, simple methods have been applied and developed to combine C-V and C-f measurements to estimate radiation-induced oxide, interface, and border trap densities in MOS capacitors. The change in capacitance with frequency enables estimates of border-trap densities before and after irradiation using assumptions and analyses that are similar to ones validated in detailed studies on MOS transistors.
Then, C-V and C-f measurements have been applied to estimate radiation-induced trapped- charge densities in multi-fin Ge and InGaAs capacitors with high-K gate dielectrics. Trapped charge densities are below 2×1011/cm2 at doses up to 1.0 Mrad(SiO2) for the Ge pMOS multi-fin devices; capacitor results are consistent with transistor results. From C-f measurements, we infer that as-processed border-trap charge densities in these devices are ~ 1011/cm2.
Higher border-trap densities are found in as-processed, development-stage InGaAs capacitors.
For these devices, charge trapping in transistors was greater than that observed in capacitors.
These results further support the potential use of Ge pMOS devices in electronics for space systems, and provide useful insight for the future development of InGaAs-based FinFETs.
In summary, the radiation response of Ge pMOS FinFETs and InGaAs MOS FinFETs has been evaluated in detail. Capacitance-frequency (C-f) measurements are used to provide lower- bound estimates of border-trap densities on these devices. These results show the utility of C-f measurements in characterizing defect densities in MOS capacitors, particularly when large border-trap densities exist.
REFERENCES
[1] P. S. Winokur, J. R. Schwank, P. J. McWhorter, P. V. Dressendorfer, and D. C. Turpin, “Correlating the radiation response of MOS capacitors and transistors,” IEEE Trans. Nucl. Sci. vol. 31, pp. 1453- 1460, 1984.
[2] T. R. Oldham and F. B. McLean, “Total ionizing dose effects in MOS oxides and devices,” IEEE Trans. Nucl. Sci., vol. 50, no. 3, pp. 483–499, Jun. 2003.
[3] J. R. Schwank, M. R. Shaneyfelt, D. M. Fleetwood, J. A. Felix, P. E. Dodd, P. Paillet, and V. Ferlet- Cavrois, “Radiation effects in MOS oxides,” IEEE Trans. Nucl. Sci., vol. 55, no. 4, pp. 1833–1853, Aug. 2008.
[4] J. P. Colinge, A. Orozco, J. Rudee, et al., “Radiation dose effects in tri-gate SOI MOS transistors,”
IEEE Trans. Nucl. Sci., vol. 53, no. 6, pp. 3237–3241, Dec. 2006.
[5] J. P. Colinge, FinFETs and Other Multi-Gate Transistors. New York: Springer-Verlag, 2008.
[6] F. El-Mamouni, E. X. Zhang, R. D. Schrimpf, et al., “Fin-width dependence of ionizing radiation- induced subthreshold-swing degradation in 100-nm gate-length finFETs,” IEEE Trans. Nucl. Sci., vol. 56, no. 6, pp. 3250–3255, Dec. 2009.
[7] E. Simoen et al., “Challenges and opportunities in advanced Ge pMOSFETs,” Mater. Sci. Semicond.
Process, vol. 15, no. 6, pp. 588–600, 2012.
[8] E. Simoen, M. Gaillardin, P. Paillet, et al., “Radiation effects in advanced multiple gate and silicon- on insulator transistors,” IEEE Trans. Nucl. Sci., vol. 60, no. 3, pp. 1970-1991, Aug. 2013.
[9] I. Chatterjee, E. X. Zhang, B. L. Bhuva, et al., “Geometry dependence of total-dose effects in bulk FinFETs,” IEEE Trans. Nucl. Sci., vol. 61, no. 6, pp. 2951-2958, Dec. 2014.
[10] J. Mitard, L. Witters, H. Arimura, et al., “First demonstration of 15 nm-WFIN inversion-mode relaxed-Germanium n-FinFETs with Si-cap free RMG and NiSiGe source/drain,” in Proc. IEEE IEDM, Dec. 2014, pp. 16.5.1–16.5.4.
[11] L. Witters, J. Mitard, R. Loo, et al., “Strained germanium quantum well p-FinFETs fabricated on 45 nm Fin pitch using replacement channel, replacement metal gate and germanide-free local interconnect,” 2015 Symposium on VLSI Technology Digest, pp. T56-57.
[12] J. Mitard, L. Witters, G. Eneman, et al., “Strained Ge quantum well pMOS FinFETs fabricated on in situ phosphorus-doped SiGe strain relaxed buffer layers using a replacement fin process,” in Proc.
IEDM, pp. 20-4, Dec. 2013.
[13] G. X. Duan, C. X. Zhang, E. X. Zhang, et al., “Bias dependence of total ionizing dose effects in SiGe-SiO2/HfO2 pMOS FinFETs,” IEEE Trans. Nucl. Sci., vol. 61, no. 6, pp. 2834-2838, Dec. 2014.
[14] E. X. Zhang, D. M. Fleetwood, J. A. Hachtel, et al., “Total ionizing dose effects on strained Ge pMOS FinFETs on bulk Si,” IEEE Trans. Nucl. Sci., vol. 64, no. 1, Jan. 2017, vol. 64, no. 1, pp.
226-232, Jan. 2017.
[15] D. M. Fleetwood, “Total ionizing dose effects in MOS and low-dose-rate sensitive linear-bipolar devices,” IEEE Trans. Nucl. Sci., vol. 60, no. 3, pp. 1706-1730, Aug. 2013.
[16] D. M. Fleetwood, “1/f noise and defects in microelectronic materials and devices,” IEEE Trans.
Nucl. Sci., vol. 62, no. 4, pp. 1462-1486, Aug. 2015.
[17] D. M. Fleetwood, W. L. Warren, J. R. Schwank, P. S. Winokur, M. R. Shaneyfelt, and L. C. Riewe,
“Effects of interface traps and border traps on MOS postirradiation annealing response,” IEEE Trans. Nucl. Sci., vol. 42, no. 6, pp. 1698-1707, Dec. 1995.
[18] D. M. Fleetwood and N. S. Saks, “Oxide, interface, and border traps in thermal, N2O, and N2O- nitrided oxides,” J. Appl. Phys., vol. 79, pp. 1583-1594, 1996.
[19] D. M. Fleetwood, “Fast and slow border traps in MOS devices,” IEEE Trans. Nucl. Sci., vol. 43, no.
3, pp. 779-786, Jun. 1996.
[20] D. K. Schroder, Semiconductor material and device characterization. John Wiley & Sons, 2006.
[21] S. F. Bent, “Organic functionalization of group IV semiconductor surfaces: principles, examples, applications, and prospects,” Surface Science, vol. 500, no. 1, pp. 879-903, Mar. 2002.
[22] J. R. Schwank, “Basic mechanisms of radiation effects in the natural space radiation environment,”
Sandia National Labs., no. SAND--94-1580C; CONF-940726-12., Jun. 1994.
[23] X. L. Hu, J. K. Gui and C. Z. Zhao, “Ionizing radiation testing system for emerging semiconductor materials and devices,” Appl. Mechanics and Mater., vol. 120, pp. 495-498, Oct. 2011.
[24] R. C. Hughes, “Hole mobility and transport in thin SiO2 films,” Appl. Phys. Lett., vol. 26, no. 8, pp.
436-438, Apr. 1975.
[25] P. S. Winokur, H. E. Boesch, Jr., J. M. McGarrity, and F. B. McLean, “Two-stage process for buildup of radiation-induced interface states,” J. Appl. Phys., vol. 50, no. 5, pp. 3492-3494, May 1979.
[26] D. M. Fleetwood, “Border traps in MOS devices,” IEEE Trans. Nucl. Sci., vol. 39, no. 2, pp. 269–
271, Dec. 1992.
[27] S. Datta, “Recent advances in high performance CMOS transistors: from planar to nonplanar,”
Electrochem. Soc. Inter., vol. 22, no. 1, pp. 41-46, 2013.
[28] M. Heyns and W. Tsai, “Ultimate scaling of CMOS logic devices with Ge and III-V materials,” MRS Bulletin, vol. 34, no. 7, pp. 485-488, Jul. 2009.
[29] C. Zhao et al., “Hysteresis in lanthanide aluminum oxides observed by fast pulse CV measurement,” Mater., vol. 7, no. 10, pp. 6965-6981, Oct. 2014.
[30] Z. Xu et al., “Polarity effect on the temperature dependence of leakage current through HfO2/SiO2
gate dielectric stacks,” Appl. Phys. Lett., vol. 80, no. 11, pp. 1975-1977, Mar. 2002.
[31] B. H. Lee et al., “Thermal stability and electrical characteristics of ultrathin hafnium oxide gate dielectric reoxidized with rapid thermal annealing,” Appl. Phys. Lett., vol. 76, no. 14, pp. 1926-1928, Mar. 2000.
[32] G. Ribes et al., “Review on high-k dielectrics reliability issues,” IEEE Trans. Device and Mater.
Reliab., vol. 5, no. 1, pp. 5-19, Jun. 2005.
[33] L. W. Massengill et al., “Heavy-ion-induced breakdown in ultra-thin gate oxides and high-k dielectrics,” IEEE Trans. Nucl. Sci., vol. 48, no. 6, pp. 1904-1912, Dec. 2001.
[34] H. L. Shang et al., “Electrical characterization of germanium p-channel MOSFETs,” IEEE Electron Device Lett., vol. 24, no. 4, pp. 441–444, Jun. 2003.
[35] Y. Yuan, L. Wang, B. Yu, et al., “A distributed model for border traps in Al2O3-InGaAs MOS devices,” IEEE Electron Device Lett., vol. 32, no. 4, pp. 485–487, Apr. 2011.
[36] N. Tugluoglu, et al., “Determination of the interface state density of the In/p-Si Schottky diode by conductance and capacitance-frequency characteristics,” Physical B, vol. 393, no. 1-2, pp. 56-60, Apr. 2007.
[37] T. R. Weatherford and W. T. Anderson, Jr, “Historical perspective on radiation effects in III-V devices,” IEEE Trans. Nucl. Sci., vol. 50, no. 3, pp. 704-710, Jun. 2003.
[38] J. A. del Alamo, “Nanometre-scale electronics with III-V compound semiconductors,” Nature, vol.
479, pp. 317-323, Nov. 2011.
[39] A. Vais, J. Franco, et al., “A new quality metric for III–V/High-k MOS gate stacks based on the frequency dispersion of accumulation capacitance and the CET,” IEEE Electron Devices Lett., vol.
38, no. 3, pp. 318-321, Mar. 2017.
[40] N. Waldron et al., “An InGaAs/InP quantum well FinFET using the replacement fin process integrated in an RMG flow on 300 mm Si substrates,” Digest of Technical Papers – Sympos. VLSI Technology, Jun. 2014.
[41] J. A. Appels et al., “Local oxidation of silicon and its application in semiconductor device technology,” Phillips Res. Rep., vol. 25, no. 2, pp. 118-132, Apr. 1970.
[42] M. R. Shaneyfelt et al., “Challenges in hardening technologies using shallow-trench isolation,” IEEE Trans. Nucl. Sci., vol. 45, no. 6, pp. 2584-2592, Dec. 1998.
[43] J. P. Colinge and C. A. Colinge, Physics of semiconductor devices. Springer Science & Business Media, 2005.
[44] D. M. Fleetwood, P. S. Winokur, L. J. Lorence, Jr., W. Beezhold, P. V. Dressendorfer, and J. R.
Schwank, “The response of MOS devices to dose-enhanced low-energy radiation,” IEEE Trans.
Nucl. Sci., vol. 33, no. 6, pp. 1245-1251, Dec. 1986.
[45] D. M. Fleetwood, P. S. Winokur, R. A. Reber, Jr., et al., “Effects of oxide traps, interface traps, and
‘border traps’ on metal-oxide-semiconductor devices,” J. Appl. Phys., vol. 73, pp. 5058-5074, Jan.
1993.
[46] P. M. Lenahan and P. V. Dressendorfer, “Hole traps and trivalent silicon centers in MOS devices,” J.
Appl. Phys., vol. 55, no. 10, pp. 3495-3499, May 1984.
[47] D. M. Fleetwood, “Long-term annealing study of midgap charge neutrality,” Appl. Phys. Lett., vol.
60, pp. 2883-2885, 1992.
[48] D. M. Fleetwood, M. R. Shaneyfelt, and J. R. Schwank, “Estimating oxide-trap, interface-trap, and border-trap charge densities in MOS transistors,” Appl. Phys. Lett., vol. 64, no. 15, pp. 1965-1967, Apr. 1994.
[49] D. M. Fleetwood, M. R. Shaneyfelt, W. L. Warren, J. R. Schwank, T. L. Meisenheimer, and P. S.
Winokur, “Border traps: Issues for MOS radiation response and long-term reliability,”
Microelectron. Reliab., vol. 35, no. 3, pp. 403-428, Mar. 1995.
[50] R. E. Paulsen, R. R. Siergiej, M. L. French, and M. H. White, “Observation of near-interface oxide traps with the charge pumping technique,” IEEE Electron Device Lett., vol. 13, no. 12, pp. 627-629, Dec. 1992.