Chapter 2 Signal Integrity in Broadband Communications 10
2.4 Sources of Jitter in Communication Links
2.4.1 Transmitter Jitter
One of first and most important sources of timing jitter is the transmitter. The data are multiplexed in the transmitter with a bit rate clock. As discussed for the receiver CDR, any phase noise on the transmit clock translates into timing jitter. Therefore, understanding the generation and limits of transmit clock phase noise is worthwhile. Typically a PLL locks the on-chip transmit clock to a low phase noise reference. Current technology relies on high-quality crystals to provide a frequency reference. In addition to low phase noise, crystal oscillators (XO) have low frequency drift due to temperature and aging. However, XO are limited in terms of the frequency of operation, and the highest frequency crystals are available in the 155MHz-660MHz range for communication applications.
The operation of the frequency multiplying PLL, often called a clock multiplier unit (CMU), is illustrated in Figure 2.21. The reference is compared to the high-frequency transmit clock by dividing the frequency. This divider as well as the implementation of the phase detector are the primary differences between the CMU and the CDR PLL. The closed loop transfer function from the reference input to the PLL output is similar to (2.25), except that the divider impacts the phase feedback dynamics:
, (2.48)
where N is the frequency ratio of the transmitter clock and the reference frequency, ωb = Nωref. Note that H(s) is defined in (2.32), where ωn is also reduced by N. The transfer function in (2.48) and phase noise of the reference XO determine the transmit clock jitter:
Figure 2.21 Phase-locked loop for clock multiplication. A low-phase noise crystal oscillator is used to reduce the phase noise of a 10GHz VCO.
ΦCMU( )s Φref( )s
--- = NH s( )
. (2.49) Since phase noise of the reference is generally not cyclostationarity [74], the Wiener-Khinchin theorem relates the phase noise PSD to the output timing jitter as in (2.37). The phase noise PSD describing the reference oscillator can be modeled with (2.34), i.e. Sφref = cXO(fref/f)2. With (2.44), the output cycle-to-cycle timing jitter is calcu- lated using (2.49):
. (2.50)
The linear growth of the variance in (2.50) indicates that the timing jitter is, after long enough, limited by the 1/f2 behavior of the reference, and the frequency multiplication amplifies this affect. On short time scales,
. (2.51)
Since the ωn is scaled by N, the variance of (2.51) increases as N. Comparing the timing jitter to the bit period demonstrates the potential eye closure in the serial link indicating that margin is lost to transmit jitter as the data rate increases.
Previous transmitter jitter for SONET applications are summarized Table 2.1. The results at 10Gb/s indicate that the rms jitter is around 400fs, small compared to the 100ps bit period. At 40Gb/s, the rms jitter increases to around 600fs, while the bit period decreases to 25ps. The peak-to-peak jitter increases to around 4ps, one-sixth of the bit period. This decreasing timing margin emphasizes the future jitter challenges in broadband communication.
Next, random jitter accumulates through the output buffers and drivers. As discussed in Section 2.2.4, jitter is generated through the translation of voltage noise to timing deviation during the finite switching time of the transistor stages. This effect is illustrated
Sφ
CMU( )f N2 H f( )2Sφ
ref( )f 1–H( )f 2Sφ
VCO( )f +
=
σ∆2,CMU( )τ N2cXO τ 1 2ωn --- 1–e
τ – ωn
2
--- τωn 2
--- 3 τωn 2 --- sin +
⎝cos ⎠
⎛ ⎞
⎝ ⎠
⎜ ⎟
⎜ ⎟
⎛ ⎞
+
⎝ ⎠
⎜ ⎟
⎜ ⎟
⎛ ⎞
=
σ∆2,CMU( )τ N2cXO 3ωnτ2 ---4
⎝ ⎠
⎜ ⎟
⎛ ⎞
≈
in Figure 2.22. Each buffer increases in size with respect to the previous stage until the output load, the 50Ohm transmission line impedance, can be driven. This requires a large drive current at the final stage and, therefore, large transistors to switch this current.
Early studies on jitter generation in buffer stages focused on the use of ring oscillators [71][72]. In [71], McNeill demonstrates that for a bipolar stage, the additive rms jitter is
, (2.52)
where rbx is the effective input (base) noise resistance, CL is the buffer load capacitance, and Itail is the differential pair current. In most designs, the slew rate, Itail/CL, is essentially constant and the variance of the buffer jitter depends on the number of stages.
Table 2.1: Recently Recorded Transmitter Jitter in SONET Transceivers
Reference Frequency RMS Jitter Peak-to-Peak Jitter
Cao et al [79] 10Gb/s 600fs 6.5ps
Hendrickson et al [80] 10Gb/s N/A 3ps-5.1ps
Muthali et al [81] 10Gb/s 440fs 1.8ps
Werker et al [82] 10Gb/s 200fs 2.0ps
Meghelli et al [83] 40Gb/s 590fs 3.4ps
Meghelli [84] 40Gb/s 600fs 4.6ps
Kim et al [85] 40Gb/s 650fs 4.9ps
Figure 2.22 Chain of buffers and line driver in transmitter. Each stage contributes additional random jitter due to thermal sources in the MOS devices and resistors.
σbuffer qCLrbx 3Itail ---
=
Weigandt expanded the first-order analysis of McNeill to consider the jitter in MOS stages with a time-varying noise model for the transistor switching [72]. The buffer jitter is determined to increase with
, (2.53)
where ξ2 = 2( γp+ γnav) is the noise multiplication factor that depends on the MOS noise factor, γ, for p- and n- MOS devices, and av = gmRL, the small signal gain. Notably, the difference between (2.52) and (2.53) is that the slew rateis not proportional to the rms jitter.
For example, the final output stage might drive a 500mV signal swing on the transmission line. In current fabrication technology, the total capacitance of the MOS parasitics and bond pad capacitance is around 50fF. Driver gain is close to unity and, therefore, the rms jitter is roughly 2fs, quite small compared to the transmit clock jitter.
In summary, the RJ components in the transmitter can be traced to the phase noise of the bit rate clock and the conversion of thermal noise to buffer jitter:
. (2.54)
Deterministic jitter sources can also be found in the transmitter, in particular when sub-rate clocks are used to multiplex the data to the bit rate. Pulse-width distortion in these cases increases the timing deviation on one of the multiplexer paths and causes a DJ in the data eye [30].