Materials for Advanced Packaging

Lee, PhD/Professor of Electrical and Computer Engineering, University of California, Irvine, 2226 Engineering Gateway Building, Irvine, CA 92697-2660. School of Engineering, University of California, Optoelectronics Packaging & Materials Labs, 916 Engineering Tower, University of California, Irvine, CA 92697-2575.

Introduction

Categories of 3D Integration Technologies

In this category of 3D integration, individual wafers are first fabricated and then the wafers or ICs are assembled in 3D with via thru-Si which provide Fig. If the interconnections are made via thru-Si, the technology is categorized as 3D IC-Stacking (second category) and if the interconnections are made outside the cover, then it is categorized as 3D-Packaging.

Motivation for 3D Integration

System performance is much better with 3D integration than either of the two 2D technologies, SOC and MCM. One of the main factors contributing to the better performance of 3D technologies is that the longer interconnects in 2D are replaced by much shorter vertical interconnects in 3D as shown.

Table 1.1 shows the relative ranking of the three technology options for each of these factors

Description of Technologies

Fig.1.21Ziptronix's Waferbonding technology using DirectBondInterconnect (DBI): (a) detailed process and (b) cross-sectional SEM micrograph [32]. i) the metal bonding line is thermally conductive, allowing heat to be more easily dissipated to the side of the chip or transferred vertically through vias, and (ii) metal bonding can be used for the dual function of both mechanical support and electrical interconnection between the ICs. After removal of the damage layer by wet etching, the wafer strength increases, as shown in Fig.

Fig. 1.12 3D On-chip integration techniques: (a) Beam Recrystllization, (b) Silicon Epitaxial Growth, and (c) Solid Phase Crystallization [5]

Main Issues in 3D Integration Technologies .1 Issues in 3D IC-Stacking

Issues in 3D-packaging

Although 3D packaging is the least expensive category of 3D integration, there is still a drive to further reduce costs in the consumer product application market. It has been shown in some analyzes [86] that 3D packaging can be even more cost-effective than the traditional approach.

Conclusions

Conference on 3D Architecture for Semiconductors and Packaging (sponsored by the Research Triangle Institute), Burlingame, CA, April. Conference on 3D Architecture for Semiconductors and Packaging (sponsored by the Research Triangle Institute), Burlingame, CA, October.

Adhesive Bonding Techniques

Adhesives in the Electronic Industries

They are widely used in the electronic industry in the form of films for flexible circuits and cables, deposited films for intermediate dielectrics, passivation and intermediate coating, substrates for multi-chip modules, adhesive pastes or tapes with some unique characteristics of low dielectric constant, high thermal stability and excellent mechanical properties [8]. Because cyanoacrylates have a very high polarity, water can act as an initiator.

Applications of Adhesives in Electronics

For double-layer tapes, they are usually made by coating solutions of polyimide precursors on copper foil or by depositing copper on polyimide films. For three-layer strips, they are formed from polyimide films coated with organic adhesive and laminated to 35 mm copper foil [4].

New Adhesives

Adhesive bonding is good for joining silicon or glass wafers at lower temperature (typically below 200 °C) and this technique is known to be less dependent on the substrate material, particles and surface roughness to be bonded. In their development, a layer was selectively applied to one of the bonding surfaces using the contact embossing method.

Direct Bonding Methods

• Anodic Bonding
• Diffusion Bonding
• Surface-Activated Bonding
• Novel Ag-to-Cu Direct Bonding

Although diffusion bonding is one of the original techniques for electronic packaging, it is now used in some specific applications. One of the main advantages of this technique is that it can be performed at room temperature or at low temperature.

Fig. 2.2 Cross section of glass-metal interface before anodic bonding [27]

Lead-Free Soldering and Bonding Processes .1 Basic Soldering Processes

The Fluxless Processes Dealing with Tin Oxides

The resulting compound SnOxFy can be easily dissolved in the molten solder and the oxide is thus removed. Chemicals other than liquids, notably formic acid vapor, have been used to treat the oxide layer [61, 62].

Oxidation-Free Fluxless Soldering Technology

The process based on the In-Ag system is interesting because it involves a transient bonding effect of the liquid phase, where the molten phase solidifies due to the solid-liquid reaction even at the bonding temperature. The reason is that a significant amount of molten Sn is squeezed out during the bonding process.

Fig. 2.9 Principle of the fluxless bonding using Sn-Ag multilayer structure [77]

Fluxless Flip Chip Interconnect Technology

Peng C-T, Liu C-M, Lin J-C et al (2004) Reliability analysis of a design for well-stepped flip chip BGA packaging. Shigetou A, Itoh T, Matsuo M et al (2006) Bump-free interconnection through ultrafine Cu electrodes by surface-activated bonding (SAB) method.

Introduction

ITRS Projections for Flip-Chip Connections

The dielectric constant of the on-chip insulators is lowered to reduce interconnect delay. Normally, one would expect the I/O induced voltage to rise as the size of the solder ball is reduced and the gap between the chip and substrate is lowered.

Electrical Modeling of I/O

The parasitic inductance of the I/O can thus be derived based on a central I/O with four surrounding cylindrical I/O. The parasitic capacitance of two cylindrical chip-to-substrate signal I/O can be calculated from Eq. Where is the center-to-center distance between two adjacent I/Os, Dis is the diameter of the I/O and His is the height.

Fig. 3.3 Circuit diagram of power/ground I/O

Mechanical Modeling

This captures the maximum load and stress that will occur at the corner of the package. The correct choice of boundary conditions is important since the nodes on the two surfaces of the disc are coupled.

Fig. 3.4 Illustrations of (a) 3-D quarter model, (b) 3-D octant model, and (c) 3-D slice model

Compliant Solder-Based I/O Structures

Peripheral-to-Flip-Chip Area Array Structures

Redistribution Using Area Array Solder I/O

Wafer-Scale Compliant I/O

The highest voltage point of the flip-chip solder joint is the intersection of the I/O and the chip surface [18]. Soldering attachment metal to the exposed side of the beam allows for bonding to the next layer of packaging.

Improved Mechanical Performance Solder Capped Structures

The bimetallic internal stress gradient in the beam causes an upward bending of the beam upon release from the surface. Applying a metal conductor to the outside of a polymer pillar could improve the flexibility of the connection structure.

Fig. 3.11 Tin bonded between two copper bumps

Solder-Free Chip-to-Substrate Interconnects

• Copper Interconnects
• Electroplated Copper Column Arrays
• Compliant Gold Bump Interconnects
• Electroless NiB Interconnects

To analyze the strength of the bond between the copper surfaces, qualitative and quantitative approaches were followed. Analysis of the quality of the copper-to-copper bonded region was shown by optical microscope analysis of.

Fig. 3.12 TEM of copper wafer bonding process using 4008C bonding and annealing temperature

Distant Future Needs and Solutions for Chip-to-Substrate Connections

Ultra-high Off-Chip Frequency and High Bandwidth Operation

One of the proposed structures includes optical connections made by polymer pins that serve as vertical optical connections, with traditional solder balls providing electrical connections. For this structure, the polymer pins on the outer surfaces are metallized (as shown in Figure 3.19).

Fig. 3.19 SEM images of dual-mode metal clad polymer pins with (a and b) Au clad and (c and d) solder plated onto structures

Microfluidic Interconnects for Thermal Management

Sitaraman, Proceedings of the International Conference on Heat, Mechanics and Thermomechanical Phenomena in Electronic Systems (2002). Sitaraman, Proceedings of InterPack, The Pacific Rim International, Intersociety, Electronic Packaging Technical/Business Conference and Exhibition (2001).

Fig. 3.21 Die backside microchannel array for microfluidic cooling

Introduction

The chapter will also describe wire splicing applications and the future of wire splicing in relation to the growing demands for extremely high density and high performance connections.

Interconnection Requirements

Using copper as the IC metallization with soft organics as the intervening dielectric layers presents challenges for first level (on-chip) interconnect processes, especially wire bonding. Copper metallization pads will require copper wire bonding or a suitable barrier layer metallization cap to allow bonding with gold or aluminum wires.

Figure 4.1 illustrates current and projected I/O number requirements with time for various types (classes) of electronic products

Bonding Principles .1 Wire Bonding Types

• Thermocompression Bonding
• Ultrasonic Bonding
• Thermosonic Bonding
• Other Techniques
• Machine Optimization

In ultrasonic bonding, the second bond must lie along the center line of the first (see Fig. Due to the addition of ultrasonic energy (causing local heat generation at the wire-pad interface), stage requirements, and capillary heat (as mentioned above) and pressure (force) we can relax.

Fig. 4.5 Number of I/O’s as a function of chip or package area for both perimeter (1 row to 4 rows) and area array interconnection points (bonding pads)

Materials .1 Bonding Wire

Bond Pads

To achieve the highest bondability in the presence of titanium, bonding temperatures must be increased significantly (>1808C), which requires the use of high-temperature dies (e.g., the gold-silicon eutectic). Certain manufacturers over the years have 'flattened' or 'minted' the thick film at the glue site using special tools placed in gluing machines.

Gold Plating

Mechanical operations such as polishing (scrubbing with an abrasive) or coining appeared to have little effect and in the case of the heavily alloyed gold, polishing significantly reduced the bonding capacity. Other plated gold phenomena such as hydrogen inclusion and film hardness can also cause bonding problems.

Pad Cleaning

The resonant frequency of a given diameter tied wire is dependent on the length and height of the loop. Again, it is a matter of the resonant frequency of the structure compared to the ultrasonic agitation frequency.

Table 4.6 Average ball bond shear strength (grams (force)) for various cleaning treatments and thermal aging conditions for thermosonically bonded 25.4 mm gold wire on 1 mm thickness aluminum (on silicon)

Testing

The ball shear test requires placing a ram (wedge-shaped tool with a flat or slightly curved face) on the major diameter of the ball. The ultrasonic wave travels through the ball or wedge bond and the bond interface on the surface of the IC.

Fig. 4.15 Wire Bond pull strength histograms for 25 mm diameter thermosonically bonded gold wire on gold thin-film metallization on highly polished alumina ceramic

Quality Assurance

Another quality assurance measure is to work with wire vendors to ensure a continuous supply of high quality wire of appropriate strength and temperament with a minimum amount of lubricants. Careful control of contact pad geometry as well as bond length and height is necessary to ensure high quality bonds.

Reliability

Intermetallics

Aluminum-gold intermetallic formation occurs naturally during the bonding process and contributes significantly to the integrity of the gold-aluminum interface. Impurities in the bond wire, on the pad metallization or at the wire bond-pad interface have been shown to cause rapid intermetallic growth and Kirkendall voiding at temperatures below those associated with normal intermetallic formation [9].

Fig. 4.22 Scanning electron photomicrographs of advanced intermetallic growth: (a) underside of ball bond with regions of intermetallic voiding (Kirkendall); (b) residual intermetallic left on bonding pad corresponding to the voided regions of the ball in

Cratering

The results of etching experiments showed that the appearance of cracks in bare silicon or in silicon dioxide (SiO2) in silicon due to incorrect bonding parameters did not occur, if the bonding machine parameters fell within the bonding window defined for the experimental setup . . A more plausible explanation would be that the additional metal would prevent the gold and aluminum ball from bonding to the underlying silicon substrate during thermosonic cleaning.

Design (Wire Spacing, Loop Height)

In ultrasonic connections, the historical deformation of the connection leg was 1.5 times the wire diameter. Today this deformation is about 1.1-1.2 times the wire diameter in thin-gauge applications.

Fig. 4.23 Scanning electron photomicrograph of ultrafine pitch (55 mm) thermosonic ball bonding.

Advanced Concepts .1 Fine Pitch

• Soft Substrates
• Higher Frequency Bonding
• Stud Bumping
• Extreme Temperature Environments

It has been shown [16] that the pad bends or warps under the influence of the adhesive force. In the Al +1% Si metallization, the bond strength increased significantly for both frequencies.

Table 4.12 Gold thermosonic ball bond diameters (in mm) in directions perpendicular (X-direction) and parallel (Y-direction) to the direction of the ultrasonic scrub on gold and aluminum 91% Si) metallizations at both 60 and 100 kHz a

Summary

Development of Ultrathin Flip Chip Assemblies for Low Profile SiP Applications,'' in Proc. Laser direct writing (LDW) technology and its applications in low temperature co-deposited ceramic (LTTC) electronics,'' in Proc.

Global Lead-Free Soldering Implementation

Summary Due to the global trend of green manufacturing, lead-free soldering is becoming the main choice of the electronics industry. Although this legislation did not specifically focus on lead, it effectively steered the Japanese industry toward a lead-free soldering process.

Prevailing Lead-Free Solder Alloys

SnZn (+Bi)

This enables the SnZnBi alloy to be a viable alternative to lead-free soldering in Japanese industry such as NEC and Panasonic. However, compared to other lead-free alloys, SnZnBi is still more reactive towards flux and oxygen, therefore it is limited in applications.

BiSn (+Ag)

Although attractive due to its low melting temperature, its high surface tension (0.768 N/m for Zn) and its high reactivity to flux and oxygen prohibit its use for electronic soldering. Addition of Bi, such as Sn89Zn8Bi3 (189–1998C), effectively reduces surface tension and reactivity, in addition to further lowering the melting temperature.

Lead-Free Solder Pastes

As for the solder ball, although Sn63 was also the best, it was quite close to the best lead-free systems. Bi58Sn42 showed a fairly poor solder ball performance, but an excellent solder appearance under lead-free systems.

Fig. 5.3 Relation between flux fraction burn-off and flux volume in a TGA study for a no-clean flux vehicle used for solder paste

Lead-Free Surface Finishes

Type of Lead-Free Surface Finishes