2.3 Lead-Free Soldering and Bonding Processes .1 Basic Soldering Processes
2.3.4 Fluxless Flip Chip Interconnect Technology
during the bonding process, the molten phase (L) dissolves enough Ag and turns into Ag2In completely. The Ag2In compound is in solid phase at the bonding temperature. Therefore, the joint solidifies during the bonding process and before cooling to room temperature. This effect is usually referred to as transient liquid phase bonding. At and beyond 3008C, Ag2In turns into g phase which remains solid until temperature reaches 6308C.
Thus, the joint produced has very high melting temperature even though it is made at 2058C.
pattern. In the first step, 0.03mm of Cr and 0.1mm of Au are deposited in a vacuum chamber as a blanket UBM and a plating seed layer. To define the solder bumps, negative SU-8 resist is coated and photolithographically pat- terned to produce cavities with nearly vertical sidewalls. The pattern has 1010 circular cavities each with a diameter of 250mm and pitch of 500mm.
Sn is electroplated in the cavities, followed immediately by a thin Au capping layer. The Au and Sn layers are plated in disc shape with composition of 98 wt.% Sn and 2 wt.% Au. The Si wafer is precisely diced into 7 mm7 mm chips. Borosilicate glass is used as the substrate because it is transparent and makes alignment easier. On the glass wafer, Cr (0.03mm) and Au (0.1mm) are deposited. Lithographic and etching processes are performed to define a 1010 array of 200 mm circular bond pads. The glass wafer is diced into 10 mm 10 mm substrates. Both the silicon chip and the glass substrate are aligned in a special fixture and held together with a static pressure of 413 kPa (60 psi). The flip chip bonding is carried out in a tube furnace in hydrogen environment. The furnace is heated until the fixture reaches 2508C and the dwell time is 3 min.
Figure 2.14(a) exhibits the optical microscope image looking into glass substrate. It shows that all the bumps are joined to Cr/Au pads with good alignment. To confirm the quality of the flip chip joints, SEM image on cross section of a bonded sample is displayed in Figure 2.14(b). The solder joints on the cross-section have very uniform thickness with nearly vertical drum shape, which indicates that solder bumps are well aligned to the Cr/Au pads on the glass substrate. The good solder joint alignment probably implies that there is some self-alignment effect during the fluxless bonding process. Figure 2.14(c) shows the backscattered electron (BSE) image on the cross section of a typical solder joint. EDX data gave an average composition of 98 at.% of Sn. The small bright spots are believed to be AuSn4grains.
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Advanced Chip-to-Substrate Connections
Paul A. Kohl, Tyler Osborn, and Ate He
Abstract Transistor scaling, shrinking the critical dimensions of the transistor, has led to continuous improvements in system performance and cost. Higher density of the transistors and larger chip size has also led to new challenges for chip-to-substrate connections. The pace of change in packaging and chip-to- substrate connections has accelerated because off-chip issues are increasingly a limiting factor in product cost and performance. Chip-to-substrate connections are challenged on many fronts, including number of signal input-output (I/O) connections, I/O that operate at high-speed, power & ground I/O, and low cost.
This chapter examines various techniques and structures that have been designed to address these challenges. The mechanical compliance and elec- trical performance modeling of the interconnect structures is important in determining the geometry, materials, and processing necessary for an applica- tion. Various approaches have been taken to satisfy both the mechanical and electrical needs for these I/O connections. Mechanically compliant structures based on traditional solder bonded connections can drastically improve thermo-mechanical reliability but may compromise electrical performance.
Additional structures improve upon the compliance of the solder ball by capping a pillar structure with solder, but still require the reliable protection of underfill. More high performance and long term improvements to satisfy both mechanical and electrical needs such as interconnects composed entirely of copper are also discussed. Finally, the future needs projected by the ITRS for ultra-high off-chip frequency and thermal management are addressed with respect to chip-to-substrate interconnects.
Keywords Input/Output
Compliant I/OCopper interconnectsSolder-freeElectronic packaging
Flip-chipP.A. Kohl (*)
School of Chemical and Biomolecular Engineering Georgia Institute of Technology Atlanta, GA 30332-0100
e-mail: [email protected]
D. Lu, C.P. Wong (eds.),Materials for Advanced Packaging,
DOI 10.1007/978-0-387-78219-5_3,ÓSpringer ScienceþBusiness Media, LLC 2009 77