There are many issues that still need to be fully resolved before 3D IC-stacking technologies can be fully commercialized. Many of the issues and their solutions are strongly dependent on the application and the technology used. Therefore each application is being individually evaluated to understand the application- specific issues. Some of the common issues that have been raised are thermal management, IC-stack yields, uncommon die size, and inadequate infrastruc- ture for design, equipment and processing.
1.3.1.1 Thermal Management
All of the initial applications envisioned for 3D IC-stacking are for micro- systems, where power dissipation is low, for example in memory modules (See Fig. 1.29) [40], logic-memory stacks [32] and image sensor read-out modules [59]. The extent of the thermal problem for applications using next generation
2rdlevel metal
10-15 micron-thick die embedded in multilayers of BCB/Cu structure
BCB Ultra-thin die
Fig. 1.53 Embedded die-stack technology [91]
of IC technologies is currently not well understood and is still being evaluated [3, 5, 14, 41, 92–95]. Some of the initial thoughts and examples are:
1. Many applications may require the use of more efficient advanced cooling concepts like micro-gap cooling as illustrated by Toshiba as illustrated in Fig. 1.54 [41].
2. Layout of the architecture and design of the functional blocks significantly affects the maximum temperature in a 3D IC-stack. This has been illustrated in the case of Logic-memory stack as illustrated in Fig. 1.55 [5]. The optimum layout involves avoiding having two heat-generating functional blocks in close proximity of each other.
3. The design layout of the vias also plays a role in minimizing the temperature of the IC-stack [93]. Smaller via pitch and additional thermal vias will allow higher heat dissipation.
Vertical interconnections on 3S LSI
Encapsulate Resin 50μm10μm
Si Die Si interposer
Encapsulate Resin 50μm10μm
Si Die Si interposer
Encapsulate Resin
Cu Through Via (10μm sq.) 20μm pitch
50μm10μm Connecting Cu Through Via
Si Die
Si interposer
“Microgap cooling” drastically enhances the cooling capability of 3D chip stacking module
Power: 100W (25W X 4 chips) Chip size: 10mm2 h
h
h h h h
Full area Cu-via bump
Micro-gap surface h=5000 W/m2K adiabatic
adiabatic interposer interposer
Partial underfill Peripheral Cu-via bump h=5000 W/m2K
4th-chip 3rd-chip 2nd-chip 1st-chip
4th-chip 3rd-chip 2nd-chip 1st-chip
coolant
Coolant (fluid)
ΔT [K] ΔT [K]
interposer interposer
Simulation of parallel cooling I/F
“Microgap cooling” drastically enhances the cooling capability of 3D chip stacking module
Power: 100W (25W X 4 chips) Chip size: 10mm2 h
h h h
h h
h h h h
Full area Cu-via bump
Micro-gap surface h=5000 W/m2K adiabatic
adiabatic interposer interposer
Partial underfill Peripheral Cu-via bump h=5000 W/m2K
4th-chip 3rd-chip 2nd-chip 1st-chip
coolant
Coolant (fluid) ΔT [K]
20 65 ΔT [K]20 65
interposer interposer
Simulation of parallel cooling I/F
Fig. 1.54 Toshiba’s Micro-gap cooling of 3D IC-stack [41]
2D 3D-1 3D-2 3D-3 3D-4
2D 3D Scheme 1 3D Scheme 2 3D Scheme 3 3D Scheme 4
L M
M L
M
L L M
L M
M L L M
200 150 100
Max. Temp. @ Si-1 Max. Temp. @ Si-2
50 0 250
Fig. 1.55 The chart shows the effect of design layout of the functional blocks on maximum temperatures in a Logic-memory stack [5]
4. Minimize the use of low thermal conductivity materials and maximize the use of high thermal conductivity materials within the stack. This is where metal-to-metal bonding like Cu-Cu and Cu-Sn-Cu has an additional advan- tage in helping with thermal management.
1.3.1.2 IC-Stack Yield
The yield for a wafer-level IC-Stack, Ystack, is Ydien, where Ydieis the yield of individual die on a wafer and n is the number of dice in the stack. Thus if die yield is 80%, the 3-die stack yield will be 51%. If the die yield is 99%, the 3-die stack yield will be 97%. Thus only high yielding dice will give high stack yield. The chip-to-chip and chip-to-wafer stacking is not affected by wafer yields because only known-good-die (KGD) are used.
One way to resolve the issue with low yielding dice in wafer-level processes is to pre-select known-good-die (KGD) and rearrange them in a wafer- format on a handling wafer [20, 25]. This concept is illustrated in Fig. 1.56.
This rearranged handling wafer with KGD can then be stacked like a regular wafer on a target wafer.
1.3.1.3 Uncommon Die Sizes
The wafer-level IC-stacking processing cannot be used if the die sizes in a stack are not the same. Thus in this case, the stacking technology is limited to 2-die or 3-die stack in pyramid-like structure. The chip-to-wafer stacking process is illustrated in Fig. 1.57 [20].
xX X
XX X X X
X
xX X
XX X X X
X
Known-good-die
Fig. 1.56 Rearranging known-good-die (KGD) from donor wafers to a handling wafer.
Rearranged handling wafer is then used to stack KGD on a target wafer [20]
1.3.1.4 Inadequate Infrastructure
Before IC-stacking processes can be commercialized, they requires an infra- structure for design, equipment and processing. Infrastructure vendors like EVG, Karl-Suss and Cadence have been increasingly putting more resources in developing 3D IC-stacking capability. Having large corporations like IBM, Intel, Infineon, Toshiba and NEC being seriously interested in the capability will further motivate some of these vendors.
1.3.1.5 Cost
3D IC-stacking technology using thru-Si via technology is an expensive tech- nology because of high capital investment as well as high direct production cost.
However, like many other technologies in the past, per unit cost will come down with technology maturation and higher production volumes. Use of high yielding ICs and wafer-level processes will further help in keeping the cost down.
1.3.2 Issues in 3D-packaging
Since 3D-packaging is already used in many applications, many issues have already been resolved. However, two main issues still remains, namely thermal management and cost.
1.3.2.1 Thermal Management
Each specific 3D-packaging technology has to be individually evaluated for thermal issues and solutions. Use of heat spreaders and heat sinks can be Fig. 1.57 IC-stacking with uncommon die sizes using the chip-to-wafer process [20]
extended to 3D in a few cases. Some systems may require exotic heat dissipation apparatus as shown in Fig. 58.
1.3.2.2 Cost
Although 3D-packaging is the lowest cost 3D integration category, there is still a push to further lower the cost in the consumer product applications market. In some analysis, it has been shown [86] that 3D-packaging can be even more cost- effective than traditional approach. In cost analysis, the higher cost of assem- bling 3d-packages can be countered by the following cost advantages:
1. Fewer discrete components have to be assembled on a board.
2. A reduction in overall packaging cost i.e. in wire-bonded die-stacks.
3. Cost savings due to the reduction in area of printed wiring board assemblies.