3.5 Distant Future Needs and Solutions for Chip-to-Substrate Connections
3.5.2 Microfluidic Interconnects for Thermal Management
reduced metal thickness, and that electrical resistance increases with metal thickness [78]. For practical use the dual-mode pin would have to be carefully designed based on the application specific electrical and mechanical perfor- mance needs.
it could allow for increased density of 3-D stacking of silicon chips and large improvements in thermal management for these systems such as System-in-a- Package type devices.
Another microfluidic cooling study performed by Zhao et al. showed that very high heat removal rates can be realized by incorporating microchannels onto both the front and backside of the silicon die [82]. Figure 3.22 shows a schematic design of the microchannels. Additionally, they showed that depos- iting a small amount of copper on the interior of the channel structures could greatly enhance the heat transfer and therefore heat removal rate [82]. Using the front and backside channel architecture, 200 W/cm2 removal rate was demonstrated.
Reference
1. S. J. Horowitz, J. J. Felten, D. J. Gerry, IEEE Transactions on Components, Hybrids, and Manufacturing Technology, vol. CHMT-2, 4, (1979) pp. 460–466
2. S. L. Khoury, D. J. Burkhard, D. P. Galloway, T. A. Scharr, Proceedings of Electronic Components and Technology Conference, vol. 1, (1990) 768–476
3. G. Pascariu, P. Cronin, D. Crowley, Proceedings of Electronics Manufacturing Technol- ogy Symposium (2003) 423–426
Fig. 3.21 Die backside microchannel array for microfluidic cooling
Fig. 3.22 Frontside and backside microfluidic cooling design
4. P. Wolflick, K. Feldmann, Proceedings of Electronics Manufacturing Technology Sym- posium (2002) 27–34
5. International Technology Roadmap for Semiconductors 2006 Update: Assembly and Packaging
6. A. Muramatsu, M. Hashimoto, H. Onodera, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Science,88, 12 (2005) 3564–3572
7. K. Shakeri, M. Bakir, J. D. Meindl, Proceedings of the IEEE SOC Conference (2004) 78–81
8. W. D. Becker, J. Eckhardt, R. W. Frech, G. A. Katopis, E. Klink, M. F. McAllister, T. G.
McNamara, P. Muench, S. R. Richter, H. H. Smith, IEEE Transactions on Components, Packaging, and Manufacturing Technology,21, 2 (1998) 157–163
9. O. P. Mandhana, IEEE Transactions on Advanced Packaging,27, 1 (2004) 107–120 10. G. A. Katopis, Proceedings of IEEE,73, 9 (1985) 1405–1415
11. C. T. Chen, J. Zhao, Q. Chen, Proceedings of Electronic Components and Technology Conference (2001) 1102–1106
12. F. W. Grover, Inductance Calculations, Working Formulas and Tables, New York:
Dover (1962)
13. G. Troster, Proceedings of Design, Automation, and Test in Europe Conference and Exhibition (1999) 423–424
14. E. C. Jordan, K. G. Balmain, Electromagnetic Waves and Radiating Systems, Second Edition, Prentice-Hall, Upper Saddle River, NJ (2003)
15. J. D. Kraus, Electromagnetics, Fourth Edition, McGraw-Hill, Hightstown, NJ (1992) 16. G. A. Rinne, P. D. Franzon, http://www.unitive.com/casestudies/pdfs/par.pdf, (accessed
January 20, 2007)
17. D. M. Pozar, Microwave Engineering, Second edition, John Wiley & Sons, New York, NY (1998)
18. A. He, T. Osborn, S. A. B. Allen, P. A. Kohl, Journal of the Electrochemical Society, SubmittedSeptember 2007
19. R. R. Tummala, Fundamentals of Microsystems Packaging, McGraw-Hill (2001) 20. Z. Zhang, C. P. Wong, IEEE Transactions on Advanced Packaging,27, 3 (2004) 515–524 21. C. Hillman, K. Rogers, A. Dasgupta, M. Pecht, R. Dusek, B. Lorence, Circuit World,25,
3 (1999) 28–38
22. Z. Zhang, S. K. Sitaraman, C. P. Wong, IEEE Transactions on Electronic Packaging Manufacturing,27, 1 (2004) 86–93
23. C. J. Zhai, Sidharth, R. Blish II, IEEE Transactions on Device and Materials Reliability, 3, 4 (2003) 207–212
24. L. L. Mercado, V. Sarihan, R. Fiorenzo, IEEE Transactions on Advanced Packaging,27, 1 (2004) 151–157
25. www.me.binghamton.edu/O.M.R.L/Facilities-2D-3DANSYS.htm (accessed February 13, 2007).
26. A. Perkins, S. K. Sitaraman, Proceedings of the Electronic Components and Technology Conference (2003) 422–430
27. A. Yeo, C. Lee, J. H. L. Pang, Proceedings of Thermal and Mechanical Simulation and Experiments in Micro-Electronics and Micro-Systems Conference (2004) 549–555 28. X. Fan, M. Pei, P. K. Bhatti, Proceedings of the Electronic Components and Technology
Conference (2006) 972–980
29. G. Wang, P. S. Ho, S. Groothuis, Microelectronics Reliability, 45 (2002) 1079–1093 30. K. Tunga, K. Kacker, R. V. Pucha, S. K. Sitaraman, Proceedings of the Electronic
Components and Technology Conference (2004) 1579–1585
31. F. C. Classe, S. K. Sitaraman, Proceedings of the Electronics Packaging Technology Conference (2004) 82–89
32. B. A. Zahn, Proceedings of the International Electronics Manufacturing Technology Symposium (2002) 274–284
33. P. Garrou, Semi Chip Scale International ’99, page D-1 (1999) 34. www.tessera.com
35. A. Longford, D. James, Presentation in Advance Packaging Conference, Semicon Europa, April (2006)
36. M. Bakir, H. Reed, H. Thacker, C. Patel, P. Kohl, K. Martin, J. Meindl, IEEE Transac- tions on Electron Devices,50, 10 (2003) 2039–2048
37. B. Dang, M. Bakir, C. Patel, H. Thacker, J. Meindl, Journal of Microelectromechanical Systems,15, 5 (2006) 523–530
38. D. Bhusari, H. Reed, M. Wedlake, A. Padovani, S. A. Bidstrup-Allen, P. A. Kohl, Journal of Microelectromechanical Systems,10, 3 (2001) 400–408
39. M. S. Bakir, H. A. Reed, A. V. Mule, P. A. Kohl, K. P. Martin, J. D. Meindl, IEEE Custom Integrated Circuits Conference (2002)
40. Q. Zhu, L. Ma, S. K. Sitaraman, Proceedings of International Conference on Thermal, Mechanics and Thermo-mechanical Phenomena in Electronic Systems (2002)
41. Q. Zhu, L. Ma, and S. K. Sitaraman, Proceedings of InterPack, The Pacific Rim Inter- national, Intersociety, Electronic Packaging Technical/Business Conference & Exhibition (2001)
42. Q. Zhu, L. Ma, and S. Sitaraman, Journal of Electronic Packaging,126, 2 (2004) 237–246 43. K. Kacker, T. Sokol, S. K. Sitaraman, Proceedings of the Electronic Components
Technology Conference (2007) 1678–1684
44. P. Arunasalam, H. Ackler, B. Sammakia, Proceedings of the Electronics Components and Technology Conference (2006) 1147–1153
45. E.B. Liao, A.A.O. Tay, S.S.T. Ang, H.H. Fend, R. Nagarajan, V. Kripesh, R. Kumar, and M.K. Iyer, Proceedings of the Electronic Components and Technology Conference (2006) 1246–1250
46. T. Wang, F. Tung, L. Foo, V. Dutta, Proceedings of the Electronic Components and Technology Conference (2001) 945–949
47. V.S. Rao, A.A.O. Tay, V. Kripesh, C.T. Lim, S.W. Yoon, Proceedings of the Electronic Packaging Technology Conference (2004) 444–449
48. R.R. Tummala, P.M. Raj, A. Aggarwal, G. Mehrotra, S.W. Koh, S. Bansal, Proceedings of the Electronic Components and Technology Conference (2006) 102–111
49. A. Aggarwal, P.M. Raj, B.W. Lee, M.J. Yim, A. Tambawala, M. Iyer, M. Swaminathan, C.P. Wong, R. Tummala, Proceedings of the Electronic Components and Technology Conference (2007) 905–913
50. A.O. Aggarwal, P.M. Raj, R.R. Tummala, IEEE Transactions on Advanced Packaging, 30, 3 (2007) 384–392
51. A. Huffman, M. Lueck, C. Bower, D. Temple, Proceedings of the Electronic Components Technology Conference (2007) 1589–1596
52. T. Iwasaki, M. Watanabe, S. Baba, Y. Hatanaka, S. Idaka, Y. Yokoyama, M. Kimura, Proceedings of the Electronic Components Technology Conference (2006) 1216–1222 53. W.B. Young, W.L. Yang, IEEE Transactions on Advanced Packaging,29, 3 (2006)
647–653
54. A. Fan, A. Rahman, R. Reif, Electrochemical and Solid-State Letters, 2, 10, (1999) 534–536
55. K. N. Chen, A. Fan, C. S. Tan, R. Reif, Journal of Electronic Materials,35, 2 (2006) 230–234
56. K. N. Chen, C. S. Tan, A. Fan, R. Reif, Journal of Electronic Materials,34, 12 (2005) 1464–1467
57. K. N. Chen, C. S. Tan, A. Fan, R. Reif, Electrochemical and Solid-State Letters,7, 1 (2004) G14–G16
58. K. N. Chen, S. M. Chang, L. C. Shen, R. Reif, Journal of Electronic Materials,35, 5 (2006) 1082–1086
59. C. S. Tan, R. Reif, Electrochemical and Solid-State Letters,8, 6 (2005) G147–G149
60. T. H. Kim, M. M. R. Howlander, T. Itoh, T. Suga, Journal of Vacuum Science and Technology A,21, 2 (2003) 449–453
61. A. Shigetou, T. Itoh, M. Matsuo, N. Hayasaka, K. Okumura, T. Suga, IEEE Transac- tions on Advanced Packaging,29, 2 (2006) 218–226
62. M. Schlesinger, M. Paunovic, Modern Electroplating, Fourth Edition, John Wiley and Sons, New York, NY (2000)
63. P. Andricacos, C. Uzoh, J. O. Dukovic, J. Horkans, H. Deligianni, IBM Journal of Research and Development,42, 5 (1998) 567–574
64. A. He, M. S. Bakir, S. A. Bidstrup, P. A. Kohl, Proceedings of the Electronic Components and Technology Conference, (2006) 29–34
65. A. He, T. Osborn, S. A. B. Allen, P. A. Kohl, Electrochemical and Solid-State Letters,9, 12 (2006)C192–C195
66. S. Gao, A. S. Holmes, IEEE Transactions on Advanced Packaging,29, 4 (2006) 725–734 67. S. Y. Kang, T. H. Ju, Y. C. Lee, Proceedings of the Electronic Components Technology
Conference (1993) 877–882
68. N. Watanabe, T. Asano, Proceedings of the Electronic Components and Technology Conference (2006) 125–130
69. N. Watanabe, T. Asano, Proceedings of the Electronic Components and Technology Conference (2007) 622–626
70. T. Yokoshima, Y. Yamaji, H. Oosato, Y. Tamura, K. Kikuchi, H. Nakagawa, M.
Aoyagi, Electrochemical and Solid-State Letters,10, 9 (2007) D92–D94
71. H. Honma, H. Watanabe, and T. Kobayashi, Journal of the Electrochemical Society,141, 7 (1994) 1791–1795
72. T. Yokoshima, S. Nakamura, D. Kaneko, T. Osaka, S. Takefusa, A. Tanaka, Journal of the Electrochemical Society,149, 8 (2002) C375–C382
73. Y. Yamaji, T. Yokoshima, H. Oosato, N. Igawa, Y. Tamura, K. Kikuchi, H. Nakagawa, M. Aoyagi, Proceedings of the Electronic Components and Technology Conference (2007) 898–904
74. W. C. Wu, R. B. Huang, H. T. Hsu, E. Y. Chang, L. H. Hsu, C. H Huang, Y. C. Hu, M. I.
Lai, Proceedings of the APMC (2005)
75. W. C. Wu, E. Y. Chang, C. H. Huang, L. S. Hsu, J. P. Starski, H. Zirath, Electronics Letters,43, 17 (2007)
76. J. D. Meindl, J. A. Davis, P. Zarkesh-Ha, C. S. Patel, K. P. Martin, P. A. Kohl, IBM Journal of Research and Development,46, 2/3 (2002) 245–263
77. D. A. B. Miller, Proceedings of the IEEE,88, 6 (2002) 728–749
78. M. S. Bakir, B. Dang, O. O. A. Ogunsola, R. Sarvari, J. D. Meindl, IEEE Transactions on Advanced Packaging,54, 9 (2007) 2426–2437
79. D.B. Tuckerman, R. F. W. Pease, IEEE Electron Device Letters,2, 5 (1981) 126–129 80. B. Dang, M. S. Bakir, J. D. Meindl, IEEE Electron Device Letters,27, 2 (2006) 117–119 81. B. Dang, P. Joseph, M. S. Bakir, T. Spencer, P. A. Kohl, J. D. Meindl, Proceedings of the
International Interconnect Technology Conference (2005) 180–182
82. M. Zhao, Z. R. Huang, Proceedings of the Electronic Components Technology Con- ference (2007) 2017–2023
Advanced Wire Bonding Technology: Materials, Methods, and Testing
Harry K. Charles
Abstract Wirebonding is the most dominant form of first-level chip or inte- gration circuit interconnect method used throughout the world-wide electro- nics industry today. Many trillion of wirebonds are made annually using automated machines. Wirebonding is reliable, flexible, and low cost when compared to other forms of first-level microelectronic interconnection. Fail- ures are typically at the single digit parts per million level or below. As the number of interconnections on the integrated circuit grows with increased functionality, the bonding pads are becoming much smaller and closer together. Similarly rigid inorganic substrates and package structures have given way to their more flexible organic counterparts. Everywhere in the microelectronic industry new applications, materials, and structures are appearing and challenging the performance and, hence, the dominance of wirebonding.
This chapter focuses on the basic wirebonding methods, the materials, and the testing techniques required to produce high quality wirebonds. It addresses the organic substrate problem, stacked chip bonding, and intercon- nection over extreme temperature ranges. Reliability of the wirebonded inter- connect is explored along with testing and control methods designed to improve bond quality. High frequency bonding and the bonding to soft substrates are given special attention. Wire properties are considered along with the changing bond shapes and sizes as the number of chip’s inputs and outputs increase. Methods for chip bumping using a wirebonding machine are also presented.
Keywords wirebonding
first-level interconnect bonding wire hightemperature and high frequency bonding
interconnection of stacked and thinned IcsH.K. Charles (*)
The Johns Hopkins University, The Johns Hopkins University, Applied Physics Laboratory, 11100 Johns Hopkins Road, Laurel, MD 20723-6099
e-mail: [email protected]
D. Lu, C.P. Wong (eds.),Materials for Advanced Packaging,
DOI 10.1007/978-0-387-78219-5_4,ÓSpringer ScienceþBusiness Media, LLC 2009 113