4.9 Advanced Concepts .1 Fine Pitch
4.9.2 Soft Substrates
Deformable or soft substrates in modern wirebonding applications are usually associated with organic based boards or layers as follows: thin-film, multilayer structures on inorganic carriers such as encountered in multichip modules (MCM-Ds); laminate-type organic constructs such as encountered in printed wiring boards, MCM-Ls and chip-on-board structures [17]; and chips mounted to unreinforced laminates and/or flexible film layers.
MCM-D modules are made using deposited dielectric and thin-film metal layers. The carrier for these deposited films is usually silicon, although highly polished ceramics have been used in the past [13]. The dielectric materials are typically spun-on layers of polyimide. Benzocyclobutene (BCB), and several
lesser-known polymers [77] also have been used. These dielectric layers usually range in thickness from 5 to 25mm (or more), with as many as six layers being reported. Metallization schemes have been gold (with suitable adhesion layers such as chromium and tungsten), copper (again with suitable adhesion layers), and aluminum. In addition to organic dielectric layer softness, metal adhesion has been a challenge and requires careful processing to ensure metal layer integrity and inner layer adhesion.
In bonding to MCM-D structures, both thermosonic ball bonding and ultrasonic wedge bonding have been used. In bonding to MCM-Ds, two major issues arise: (1) the size of the bonding pad and (2) the number and thickness of the soft layers (polyimide, BCB, etc.) under the pad. It has been shown [16] that the pad bends or cups under the application of the bonding force. This cupping is due to the compliant nature of the organic nature.
Elevated temperatures exacerbate the issue, effectively softening the polymer even more. Small bonding pads have less area over which to distribute the load and are thus more susceptible to this cupping or bending phenomenon. Pad deformations under bonding forces and the application of ultrasonic energy have been studied by Takeda, et al. [78].
Their results show that normal sized gold pads on copper traces (on poly- imide flex boards) can deform as much as 20mm under normal (but high end of the range) force and ultrasonic energy bonding conditions. They also verified that the use of a nickel underlayer (under the gold pad) can significantly reduce the deformation below 10mm for all bonding conditions. Others have noted similar deformations but the amount of deformation was smaller. In our work, for example, we have observed that for a given bonding force, the deformation increases with organic layer thickness. Pad reinforcement structures and inter- layer metallization tend to mitigate deformation. Similarly, a marked decrease in deformation was observed as the bonding force was reduced in all samples, with little or no correlation to changes in sample thickness.
In addition to unreinforced substrate materials, MCM-L and COB imple- mentations can use fiber reinforced organic matrix material such as polyimide or epoxy. The reinforcing fibers are typically glass, although materials such as Kevlar1, quartz, and Aramid1 have been used. Sometimes high-frequency circuitry is built on non-fiber reinforced substrates with very low dielectric constants such as Teflon1(polytetrafluorethylene). Most of these ‘‘laminate’’
technologies use copper metallization protected by thin layers of plated gold (usually with a nickel barrier layer under the gold). The thicknesses of both the metal and dielectric layers are larger than those of the MCM-D technology by factors of 5 for the metals and at least an order of magnitude or more for the dielectrics.
Other MCM-L implementations use fiber reinforced cores with non-rein- forced resin layers on their surfaces [37]. Such structures can employ a variety of metallization schemes put in place and patterned by a combination of thin-film deposition (MCM-D) and printed wiring board (PWB) techniques. Via fills can be plated or actually filled with conductive organic resins [35].
Wirebonding to most MCM-L substrates including those in ball-grid arrays (BGA) and chip-scale packages (CSP) is similar to bonding to PWBs provided the substrates are made with fiber-reinforced resin laminates (e.g., polyimide- glass, epoxy-glass). Direct bonding to PWBs has been done for some time in COB applications. Many problems still exist with bonding to standard PWB fiber reinforced laminates, let alone the new problems associated with reduced pad sizes, unreinforced organic layers, and different via construction techniques found in today’s MCM-Ls, BGA and CSP substrates, and integrated circuit redistribution layers. Both aluminum wedge bonds and thermosonic gold ball bonds have been used in COB applications. Wedge bonding is often preferred because it can be done without added substrate heat. Large COB assemblies will tend to warp and possibly soften if heated to or near their glass transition temperature (Tg). FR-4 (epoxy-glass) circuit boards have a Tg around 1208C, while Tg of various polymide boards exceeds 2508C. Such high-temperature resins can be thermosonically bonded provided proper substrate clamping and backside support is available for large area assemblies. Successful thermosonic bonds have been made at temperatures below 100–1108C so that even FR-4 can be bonded. Even with the thick metallizations typically encountered in the COB arena (e.g., nominally 17–35mm), anomalies can exist in wirebonding, espe- cially as pads shrink in size. Bonding to BGA and CSP flexible substrates is typically done with gold-ball bonding because of the need for controlled shape bonds and bonds that are very close to the chip edges to keep the package footprint as small as possible. Because of the small area and reduced thickness of the substrate, special care has to be exercised in the bonding process.
In addition to flexible and software substrates, two other difficult bonding situations occur: thinned die and stacked die (either thinned or not). Thinned die have been around for some time, especially in microwave applications where gallium arsenide (GaAs) microwave devices have been thinned to 100mm or less to provide better thermal performance. Gallium arsenide is more susceptible to bond cratering and to mechanically induced electrical defects than silicon. For a detailed study of cratering on silicon die, see the paper by Clatterbaugh and Charles [25]. GaAs is weaker than silicon by a factor of 2. The two major material characteristics or parameters that are most relevant to cratering have been shown to be hardness and fracture toughness. Hardness is a measure of the material resistance to deformation while fracture toughness is a measure of the energy (or stress) required to propagate an existing microcrack. The Vicker’s hardness for GaAs is 6.9 (0.6) GPa while silicon is 11.7 (1.5) GPa. In a similar vein, the fracture toughness of GaAs and silicon are 1.0j/m2 and 2.1j/m2, respectively.
Thinned silicon die are now being mounted to flexible circuit boards. Silicon die as thin as 25mm have demonstrated electrical integrity. An example of 25mm thinned die mounted to a flexible tape substrate is shown in Fig. 4.25. Wirebond- ing, because of the thinness of the die and the softness of the flexible substrate has proven difficult and techniques are under development to allow wire bonding of these ultra thin assemblies. To date most of these assemblies have been flip chipped (i.e., attachment by solder reflow, Banda, et al., 2004).
Stacked die (See Fig. 4.26) present their own set of issues, but in general, the problems involve multiple geometries in a given component package with closely spaced wirebonds that can overlap. In addition, sometimes the bonding must be done to chips that are cantilevered over another chip without a means of mechan- ical support under the bonding pad areas. Fixturing and very careful control of bonding parameters (reduced force and power, higher frequency, and tempera- ture) has allowed successful wirebonding to stacked geometries with as many as six chips. A full discussion of the details of wirebonding to stacked chips is not possible in this work, but some insight can be gained by reading Yao, et al., [88].