3.1 Introduction
3.1.2 Electrical Modeling of I/O
Chip-to-substrate electrical connections have parasitic inductance, capaci- tance, and resistance properties that degrade their performance. The magni- tude of these properties and their ultimate effect on the performance of the I/O is a function of the I/O shape, distribution, and materials. Electrically, it is most desirable to have air as the medium between the chip and substrate because of the minimal coupling induced by air. However, the local mechan- ical stress within the solder joints and at the joint between the solder and the planar surface is high. Filling the area around the solder joints with an epoxy helps to distribute the mechanical stresses and avoids the highest stress points and reduces solder fatigue. However, the high dielectric constant and loss of underfill degrades the electrical characteristics and increases cross-talk between I/O.
In general, the parasitic inductance is important for power integrity, the parasitic capacitance affects the signal integrity, and the resistance contributes to the signal RC delay and conductor loss. In the next sections, the electrical and mechanical attributes of the I/O will be evaluated.
3.1.2.1 Parasitic Inductance of Chip-to-Substrate I/O
The IR (current-resistance product) voltage drop and simultaneous switching noise (SSN) are two I/O problems involved in power distribution. SSN is induced by the current change that passes through the power distribution net- work, which is mainly due to the I/O parasitic inductance [6, 7, 8, 9]. SSN can cause problems in signal timing and integrity, resulting in false switching logic circuits [10, 11]. The voltage change due to SSN can be expressed by Eq. (3.1).
V¼LdI
dt (3:1)
Where I is the current, t is time and L is the parasitic inductance or loop inductance of the chip-to-substrate I/O. Lower power supply voltage, Vdd, reduces the noise margin V or tolerance to SSN. Therefore, the parasitic inductance of the power/ground I/Os,L, needs to be kept as low as possible in order to maintain signal integrity. The parasitic inductance is a function of the physical geometry of the power/ground interconnect, loop distance (path
between power delivery and return path), and dielectric properties of the insulator surrounding the I/O.
The self and mutual inductance of the I/O are shown in Fig. 3.2. The DC current, I, is delivered through the center (power) I/O, and returns through the four neighboring quarter-size ground I/Os, where the current in each is I/4. Only a quarter of each of the return paths is used because they each must service four power I/O. Thus, the parasitic inductance of the I/O can be derived based on a center I/O with four surrounding cylindrical I/O. The cylindrical shape (ignoring the bulge at the center of a ball) will be used to simplify the calculations and make them more appropriate for other pillar connections.
The self inductance of the I/O pillar can be calculated from Eq. (3.2).
L¼0:002H ln 4H D
3 4
104ðHÞ (3:2)
WhereHis height of the pillar andDis diameter [12]. The mutual inductance between two I/O can be calculated from Eq. (3.3).
M¼0:002H ln H d þ
ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 1þH2 d2
r !
ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 1þd2
H2 r
þ d H
" #
104ðHÞ (3:3) Fig. 3.2 Chip-to-substrate
power and ground I/O layout
Here,dis defined as the distance between the center points of two I/O as shown in Fig. 3.2 [12]. The four ground pillars have the same height as the center power pillar, but only 1/4 the cross-sectional area. As a result, the resistance of the ground pillar is four times that of the center pillar. The voltage drop within the full circuit (delivery and return path) can be divided into two parts: the voltage drop within the power I/O and the voltage drop within the ground I/O as shown in Eq. (3.4) and Fig. 3.3.
Vcircuit¼VpowerþVground (3:4)
For the full circuit, the voltage drop equals the product of current times the complex impedanceZcircuit, Eq. (3.5). The impedance of the circuit, Fig. 3.3, can be expressed by Eq. (3.6). If the resistance of the center power I/O is R, then the total resistance of the circuit is 2R giving Eq. (3.7).
Vcircuit¼IZcircuit (3:5)
Zcircuit¼Rcircuitþj!Lparasitic (3:6)
Vcircuit¼2IRþj!ILparasitic (3:7)
Where Vcircuit is the voltage drop in the circuit (Fig. 3.3), Zcircuit is the overall complex impedance,Rcircuitis the resistance,!is angular frequency,j is the imaginary unit (the square root of –1), and Lparasitic is the parasitic inductance.
I
1/4 I
1/4 I
1/4 I
R 4R 4R 4R 4R
Lpower Lground Lground Lground Lground
Power I/O
Ground I/O
Ground I/O
Ground I/O
Ground I/O V
+
−
Fig. 3.3 Circuit diagram of power/ground I/O
Equations (3.8), (3.9), (3.10) and (3.11) express the voltage and impedance for the center power I/O shown in Fig. 3.2.
Vpower¼IZpower (3:8)
Zpower¼Rpowerþj!Lpower eff (3:9)
Lpower eff ¼Lpower41
4M1 (3:10)
Vpower¼IRþj! ILpower41 4IM1
(3:11) WhereVpoweris the voltage drop in the power I/O,Zpoweris the impedance, Rpoweris the resistance,Lpoweris the self inductance,M1is the mutual induc- tance between the power I/O and an adjacent ground I/O, andLpower_effis the total effective inductance of the power I/O. The same procedure can be used for each ground I/O, yielding Eq. (3.12).
Vground¼1
4I4Rþj! 1
4ILgroundþ1
4IM3þ21
4IM2IM1
(3:12) WhereVgroundis the voltage drop in one ground I/O,Lgroundis the self induc- tance,M2is the mutual inductance between the two nearest ground I/Os, and M3is the mutual inductance between the two ground I/Os at opposite corners of the four I/O surrounding the center power I/O. Substitution of Eqs. (3.11) and (3.12) into Eq. (3.7) yields a solution for the total parasitic inductance, Eq. (3.13).
Lparasitic¼Lpowerþ1
4Lground2M1þ1 2M2þ1
4M3 (3:13)
3.1.2.2 Parasitic I/O Capacitance
The parasitic capacitance will degrade the signal integrity by inducing crosstalk between adjacent I/O and by causing signal delay due to the RC product.
Although the absolute value of the parasitic capacitance and the resistance of chip-to-substrate I/Os are small compared to the on-chip interconnect, the overall system performance will benefit from lower off-chip RC delays [13].
The capacitance is also needed to calculate the characteristic impedance (Section 3.1.2.3) of the chip-to-substrate I/O since a mismatch in the character- istic impedance between the chip and substrate could result in reflective losses for high frequency signals.
The parasitic capacitance of two cylindrical chip-to-substrate signal I/O can be calculated from Eq. (3.14) through a lumped-element circuit for high frequency signals [14, 15].
C¼ p"0"r ln Ddþ ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
ðDdÞ21
q H (3:14)
Whered is the center-to-center distance between two adjacent I/O, Dis the diameter of the I/O, andHis the height. For reference, the parasitic capacitance of a 125mm diameter eutectic solder bumps was measured to be 8.8 fF [16].
3.1.2.3 Characteristic Impedance
The characteristic impedance is defined by Eq. (3.15) [17] [q].
Z0¼
ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi Rþj!L Gþj!C s
ðÞ (3:15)
WhereGis the shunt conductance due to dielectric loss, Eq. (3.16),Lis the self- inductance of the two copper pillars, Eq. (3.17),Ris the resistance, Eq. (3.16), andRsis the surface resistance of the pillars.
G¼ p!"00 ln Ddþ
ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ðDdÞ21
q HðSÞ (3:16)
L¼0r p ln d
Dþ
ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi d D
2
1 2 s
4
3
5HðHÞ (3:17)
R¼2Rs
pDHðÞ (3:18)
Where0is the permeability of vacuum, andris the relative permeability, and
"’’ is the imaginary part of the complex permittivity. For electrically isolated I/O, the shunt conductance,G, is essentially zero since the insulator between pillars is non-conductive. Equation (3.15) can be further simplified by compar- ing the magnitude ofRand!L.Rcan be calculated from the lumped resistance, Eq. (3.16). The surface resistance can be calculated from its definition Eq. (3.17).
Rs¼ 1
s (3:19)
Whereis the conductivity andsis the skin depth is defined by Eq. (3.20) [17].
s¼ ffiffiffiffiffiffiffiffiffi
2
! s
¼
ffiffiffiffiffiffiffiffiffiffiffiffi 1 pf0 s
(3:20) The impedance of the I/O may not match the remainder of the circuit. However, that may be acceptable because the load impedance dominates the circuit impedance since the I/O length is so short [18].