A packaged low noise high speed regulated cascode transimpedance amplifier using a 0.6 m N well CMOS technology

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A packaged low-noise high-speed regulated cascode transimpedance amplifier using a 0.6 µµ m N-well CMOS technology

Sung Min Park and C. Toumazou Dept. of Electrical and Electronic Engineering Imperial College of Science, Technology and Medicine

London SW7 2BT, UK Email : [email protected]

Abstract

Regulated cascode (RGC) techniques are applied to achieve better isolation of the large input parasitic capacitance in a front-end preamplifier for optical receiver applications, since the RGC circuit behaves like a common-gate transistor with large transconductance comparable to GaAs MESFET. The input resistance of the RGC circuit becomes smaller by the amount of the voltage-gain of the local feedback stage than that of a conventional common-gate input stage. Hence the RGC circuit gives a virtual-ground input impedance and better isolates the input parasitics. With this very low input impedance characteristic, a RGC transimpedance amplifier is realized with a 0.6µm digital CMOS process. This amplifier is packaged in a MQFP package, mounted on a copper PC-board, and housed in an aluminum metal box. The measured results demonstrate 300MHz bandwidth, 57.7dBΩ transimpedance gain, 10pA / Hz average noise current spectral density with

±6V power supply.

1. Introduction

For realizing VLSI and high frequency analogue circuits, it is desirable to simultaneously achieve high speed and accuracy, high gain and dynamic range, and low voltage and power consumption. However, these pairs of requirements lead to conflict and therefore need optimization. For example, short channel-length transistors are required for high speed CMOS circuits with low power supply voltage. But exploiting the minimum-size transistors gives noticeable channel- length modulation and carrier-multiplication at relatively low voltages. This results in reduction of the maximum achievable gain from the transistors. On the other hand, high gain and high accuracy with low power consumption requires long and wide channel transistors.

But these transistors result in lower speed. However, there is currently a trend towards scaling down the

minimum size of the channel-length, even though this leads to reduction of the MAG (maximum achievable gain) and of the dynamic range of transistors. Novel circuit methodologies are required in order to overcome these conflicts.

In this paper, we present a transimpedance amplifier realized with a 0.6µm CMOS technology for optical receiver applications, exploiting a regulated cascode technique at the input stage. According to [1-3], the regulated cascode (or RGC) circuits with minimum channel-length can be applied to simultaneously achieve high speed, high gain, wide dynamic range, and low power consumption. A transimpedance amplifier is preferred as a front-end preamplifier for optical receiver applications and several technologies have been successfully utilized. Among those, there have been particular interests in the use of CMOS technologies because of low power, low cost, and high integration level characteristics.

2. Regulated cascode (RGC) input stage

The regulated cascode (RGC) configuration [1] is known to provide high output impedance and wide output voltage range. In this section, another characteristic of the RGC stage (which is the very low input impedance characteristic) is studied and will be exploited to develop a preamplifier for optical receiver applications.

Figure 1 shows the schematic diagram of a regulated cascode (RGC) input stage with a photodiode as a detector. A transistor of the current mode RGC circuit is replaced with a resistor R_s and the photodiode is connected to Rs in parallel. The voltage output of the RGC circuit is drawn from the drain of M1. The local feedback stage (MB and R_B) helps the biasing of the input transistor and makes the input node (node1) sit at virtual-ground. This local feedback can be qualitatively explained as below. When the current of M1 increases, the voltage at the node1 increases and therefore the drain current of MB increases. Then, the voltage at the node2 reduces and this reduces the drain current of M1.

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Small signal analysis shows that the input resistance of the RGC stage is given by,

( )

m

(

mB B

)

in g g R

Z ≅ +

1 0 1

1

(1) where

(

1+gmBRB

)

is the voltage gain of the local feedback stage (MB and RB).

Comparison with a conventional CG input stage shows that the input resistance of the RGC input stage is

(

1+gmBRB

)

times smaller, thus giving a virtual-ground input. This isolates more effectively than the CG input stage the large input parasitics including the photodiode capacitance (Cpd). Even at high frequencies, the dependence on the capacitance (Cpd) is reduced by the voltage gain. Therefore, it can be said that the RGC circuit behaves like a common-gate transistor with large transconductance (Gm) of

(

mB B

)

m

m g g R

G = ₁1+ . (2)

However, it should be noted that a zero appears due to the local feedback stage and this zero causes a peaking in the frequency response at the frequency of

(

^gs ^gdB

)

B

peak R C C

f = +

2 1

1

π ^. ⁽³⁾

In order to shift the peaking at much higher frequency than the operation frequency of interest, the gate-width of M1 and the resistance RB should be minimized according to (3). The minimization of the gate-width (W1) is allowable because the transconductance gm1 need not to be large due to the local feedback effect shown in (2). Also the resistance RB can be minimized by increasing the bias drain current MB for the same voltage gain of the local feedback stage.

Due to the large voltage gain

(

1+gmBRB

)

, the RGC input stage may be considered to be a single-pole system and the -3dB frequency of the RGC circuit is given by,

1 1 ,

3 2

1

d RGCinput

dB RC

f⁻ ^≅ π ⁽⁴⁾

where Cd1 is the total drain capacitance of M1.

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Meanwhile, the -3dB frequency of a CG input stage is given by,

(

1

)

1 ,

3 2 _pd _s

m CGinput

dB C C

f g

≅ +

− π ^. ⁽⁵⁾

where Cs1 represents the total source capacitance of M1.

Comparing (4) with (5), the RGC input stage has a potential for wider bandwidth than the CG input stage.

With these advantages of the RGC input stage, a novel regulated cascode transimpedance amplifier is designed.

3. RGC transimpedance amplifier

Figure 2 shows the schematic diagram of the RGC TIA.

Since the input impedance of the RGC input stage is small enough to isolate the large input capacitance from the -3dB bandwidth determination, it is not advantageous applying the negative feedback to the virtual-ground input node. Rather, the feedback should be applied to the high impedance node (drain of M1) so that the dominant pole of the RGC TIA can be placed at higher frequency and thereby a wider bandwidth can be achieved.

However, it should be noted that the overload level of the circuit would be worse with this application of feedback, since smaller voltage drop across the feedback resistor results in smaller dynamic range.

A source-follower buffer stage is introduced between the RGC input stage and the voltage gain stage (M3). This common-drain stage reduces the total capacitance looking from the high impedance node and provides a potential for wider bandwidth. However, this reduces the total open-loop transimpedance gain and results in the reduction of the circuit linearity.

The closed-loop DC transimpedance gain is given by,

( )



 +

× +

= −

1 5

4 3 3 2

1 1 1

0

R R R

g Z R

f m

f c

α α α

. (6)

The dominant pole of the amplifier is determined by the time constant (τ₁) at the drain of M1 and is given by,

( ) ( )

1 2

1 1

1

1 C p C C R

R _f _d + _g + _f =

τ = ⁽⁷⁾

4 8

; <

= < > ?

@ ?

A B B

A C C

D E F F G

H I J K L M N

O P O Q R S S

T U U X Y

Z Y [ \

] ^

_ ` a ` b c

d c

b e

d e

(3)

where C_d1 and C_g2 represent the total drain capacitance of M1 and the total gate capacitance of M2, respectively.

The non-dominant pole is determined by the time constant (τ₃) at the gate of M3 and is given by,

( )

[ ]

3 3 3 3 3

2 2 2 3

1 1 1

C p R g C

C

g_m R ^s + ^gs + + ^m ^gd =





τ = ⁽⁸⁾

where C_s2 and C_g3 represent the total source capacitance of M2 and the total gate capacitance of M3, respectively.

Another pole is determined by the input time constant (τ_in) at the input node of the amplifier. Even with the large input capacitance (including the photodiode capacitance), the virtual ground input resistance makes the input pole (p_in) sit at higher frequency than other poles.

Assuming that all noise currents are uncorrelated, the equivalent noise current spectral density is approximately given by,

( )











 +

+ + +

≅ ₂ ₀_,₁

1

2 1

2

2 4 4 4 1

d m ff

gdB s ff

s

eq g

g R C C kT R

kT R

i kT ω

( )



 +



 +

+ + d B

B B

mB

gsB

pd g

R g R

C C kT

, 2 0

2 2

1 1

4 ω

(9)

where k is Boltzmann constant, T is the absolute temperature, Γ is the noise factor of MOSFET, and gd0 is the zero-bias drain conductance, and R_ff is the parallel combination of R₁ and R_f.

For minimum noise, the gate-widths of MB and M1 are optimized by differentiating (9) with respect to C_gsB and Cgs1, respectively. Also, the transconductance gm is described as in (10) because it is proportional to the gate- source junction capacitance, i.e.

(

gs gd

)

T gs

T

m f C C f C

g =²π + ≅²π . (10) The optimum gate-width of W₁ and W_B are given by,



 



 +

≅

eff ov ox

pd opt

L L C W C

3

2 (11) where C_ox is the oxide capacitance per unit area, L_ov is the overlap channel length and L_eff is the effective channel length. Here, W1 and WB are optimized to be 60µm and 120µm, respectively.

4. Chip fabrication and measured results

A test chip of the RGC transimpedance amplifier was fabricated using a 0.6µm N-Well CMOS process with single poly and 3-metal layers. It was packaged in a 100pin MQFP package. The chip area takes 0.5×0.17 mm². All devices are guarded by guard-rings in order to reduce the noise couplings. Also, the power supply lines and ground busses are separated to avoid the interference between the input RGC stage and the high current output stage. Fig. 3 shows the test fixture of the RGC packaged chip is placed on a copper PCB and housed in a cheap

metal box. Signal power enters the DUT from the left through SMA connectors and RF semi-rigid cables.

For the gain frequency response measurements, the S- parameters of the RGC TIA are measured in the frequency range of 30kHz to 6GHz using a HP8753D network analyzer with a test power level of –40dBm (which emulates a 50µA photocurrent). Then, the S- parameters are computationally converted to Z- parameters. Measured frequency response of the RGC TIA is shown in Fig. 4. The mid-band transimpedance gain of 57.7dBΩ^{(or 770}Ω) and the –3dB bandwidth of 300MHz are measured with ±6V power supply. The 3dB penalty of the transimpedance gain (61dB simulated gain) may partly be attributed to the several cable connections on PC-board and in a metal box. Besides, the limited bandwidth may be attributed to package parasitics including the large input ESD protection diode capacitance, the bonding pad capacitance, and the large pin inductance. With the variation (up to 1V) of the power supply voltages, the bandwidth remains almost constant but the transimpedance gain changes 3dB.

The noise current spectral density was measured by using an HP8560A spectrum analyser. In order to prevent outside radiation noises from adding to the noise of the chip, the PCB test fixture was housed in a metal box. The output pin of the chip is connected to the spectrum analyser through a 50Ω RF cable to measure the noise output. Figure 5 shows the measured noise current spectral density within the bandwidth (up to 300MHz) with ±6V power supply voltage. It is clearly shown that the flicker (1/f) noise contributions significantly increase the low frequency noise (below 100MHz). In Figure 5, the noise spectral density of the RGC TIA is compared with that of the CG TIA for the similar bandwidth (300MHz for RGC and 250MHz for CG). At low frequencies below 60MHz, both clearly show the significant flicker noise contributions.

However, at higher frequencies, the RGC TIA achieves lower noise than the CG TIA, confirming the super- transistor-like characteristic of the RGC input stage described in equation (2). The average noise current spectral density is measured to be 10pA / Hz. Hence, the sensitivity (S) of the RGC TIA is calculated for the BER (Bit-Error-Rate) of 10^-9 to be -28dBm, assuming that the wavelength (λ) is 850nm.

Figure 6 compares the measured input resistance of the CG and the RGC TIA in the frequency range up to 1GHz. The input resistance of the RGC stage maintains 50Ω more efficiently than the CG input stage within the measured frequency range. Even though a peaking occurs at 200MHz, the input resistance increases only up to less than 100Ω. A dip at 600MHz and another peaking at 1GHz occur, which may be attributed to the resonance of the metal box. These are also shown in the measured frequency response. Meanwhile, the CG input stage shows very high (five times larger) input resistance at low frequencies and rapidly decreases at higher frequencies. Also, the oscillation of the input resistance occurs above 100MHz, which may be attributed to the

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large input package parasitics. The RGC input stage also shows the oscillation of the input resistance at above 1GHz, which may be due to the package parasitics. This confirms that the RGC input stage can more effectively isolate the input parasitics (including the photodiode capacitance) than the CG input stage.

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5. Conclusion

We have introduced a novel regulated cascode transimpedance amplifier realized in a package with a 0.6µm digital CMOS technology. It shows that the RGC TIA has a good potential for optical receiver applications with high gain, low noise, and lower power consumption characteristics.

6. References

[1] E. Säckinger and W. Guggenbühl, “A High-Swing, High-Impedance MOS Cascade Circuit”, IEEE J. of Solid-State Circuits, vol. 25, No. 1, pp 289-298, Feb.

1990.

[2] M. Helfenstein et al., “90dB, 90MHz, 30mW OTA with the Gain-Enhancement Implemented by One- and Two-Stage Amplifiers”, Proc. IEEE ISCAS’95, Vol. 3, pp 1732-1735, 1995.

[3] S. M. Park and C. Toumazou, “Giga-hertz Low Noise CMOS Transimpedance Amplifier”, Proc. IEEE ISCAS’97, vol.1, pp 209-212, 1997.

Acknowledgments

Authors gratefully acknowledge the financial support from EPSRC project GR/L83561 (“STAR”) and the technical support of R. Thompson (Imperial college).

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