Low-Noise and Low-Power CMOS Transimpedance Amplifier for High-Speed Applications

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A CMOS Low-Noise and Low-Power Transimpedance Amplifier

Mehrdad Amirkhan Dehkordi Department of Electrical Engineering, Science and Research Branch, Islamic

Azad University, Tehran, Iran . [email protected]

Seyed Mehdi Mirsanei Department of Electrical Engineering,

Najafabad Branch, Islamic Azad University, Najafabad, Iran . [email protected]

Soorena Zohoori

Department of Electrical Engineering, Science and Research Branch, Islamic

Azad University, Tehran, Iran . orcid.org/0000-0001-5874-9573

Abstract - For specified applications of 2.5 Giga-bit-per- second, a low-noise and low-power transimpedance amplifier (TIA) is introduced here. The introduced TIA possess an active feed-forward network based on current- mirror structires beside an active load, that resonates with the capacitive load. Using 90nm CMOS library parameters, the presented TIA prvides -3dB frequency of 1.7GHz and 54.53dB ohm gain, with consumpting power of 2mW, and producing 12.6pA/√Hz input referred noise.

Keywords- Optical Receiver, Transimpedance Amplifier, Low-Noise, Low-Power.

I. INTRODUCTION

In a typical optical communication receiver system (see figure 1), the Transimpedance Amplifier (TIA) determines the basic specifications of the optical receiver such as the high-gain, low-noise and -3dB frequency [1-2], and is placed directly after the photodiode. Although designing Nano-meter CMOS TIAs are severely compromised with the noise performance, power dissipation and transimpedance gain employing low-supply voltages for Giga-bit applications, converting the weak current signal of the photodiode to a high-qualified output voltage, can still be counted as the main role of the TIAs [3].

Due to high value of parasitic capacitance of the photodiode, a large time constant, which limits the -3dB frequency, is formed directly after the photodiode. This clearly shows the importance of achieving low-value resistances at the input node for designing TIAs.

Of course, many topologies are reported in literature in order to isolate this Parasitic Capacitance (PC).

Example of those are listed here: Shunt-resistance technique [4], employing common-gate as the first stage of amplification [5], RGCs [6, 7, 8], and inverter-TIAs [10-11]. Among them, at low supply voltages RGC

structures are not capable of operating in their best way, and also common gate structures are incapable of providing sufficient Ohmic gain. Also, combination of series inductive peaking technique and active voltage- current feedback can increase the data rate of TIAs, as in [12-13].

In the presented paper, by adding a zero employing active elements to an current-mirror based amplifier, it is tried to lessen the power consumption through reducing the RC constants and hence reducing the need of high DC currents.

In the following, section 2 presents the TIA structure and the related discussions. Section 3 deals with simulation results, and conclusions are given in section 4.

II. THE PROPOSED TIA

The presented TIA and its equivalent circuit are shown in figures (2) and (3), respectively. As shown in (2), the signal is amplified once by the factor of × and then by the factor of , as the current mirror based topologies insist. Finally, these values are summed up at the out node.

The equivalent circuit suggests that M2 and M3 produce signal current by the factor of gm2, and at the output node current-mirror sources are producing signals by the factor of gm3 and gm5. Also, the active load of M6-M7 acts as an inductor in high frequencies, and as a resistor at low frequencies.

So for the open-loop gain of the circuit one can write (S→ 0):

= × + × ^×_× ⁽¹⁾

Figure 1. Transimpedance amplifier in a typical optical system

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Figure 2. The Presented TIA

Figure 3. Small Signal Equivalent Circuit of Figure (2) Consider W, L and ro as the width, length and drain- source resistance, respectively.

A diode-connected structure (M1) beside the proper feedback network helps to reduce the output and input resistances in cost of fewer transimpedance gains.

Hence, the input resistance and the total capacitance at the input are equal to: (Cgs is gate-source capacitance and Cpd is the PC of the photodiode).

= × !"× ! ^#$_% (2)

Cin= Cpd+Cgs2+Cgs3+Cgs1 ≈ Cpd (3)

Considering (2) and (3), for the input pole we have:

&' = − ^× !" . ! ^#$_%

*+,× (4)

Furthermore, an active type of inductor is used using M6 and M7, which extends the -3dB frequency.

M7-M6 can be analysed as follows writing KVL and KCL:

-./× 0./× 1 + 23/× -./= −45 (5) -./× 0./× 678× 1 + -./= −-5 (6)

Hence, neglecting the channel-length modulation for simplicity, the impedance and the active inductor’s value can be extracted.

9:=-5

45=6₇₈× 0_./× & + 1

23/+ 0./× & (7)

< = ^*^=> 678− ^! (8)

Moreover, the output impedance (S→ 0) is written as follows (channel-length modulation is neglected):

97?@=

A × B6 !D× E! ^#$_%F

(9) Hence, for the high-frequency open-loop output impedance and also the output pole can be written as follows:

97?@= 67 G67HG9:=

IJ×*_=>×K !"_I,×_IL

A ! K× J×*=>" L ," K×*=> " L× ,"D ⁽¹⁰⁾

&'7?@= −_* ^!

MNO× PQ ⁽¹¹⁾

In which output capacitance is equal to:

07?@= 0R+ 0STU+ 0S U+ 0STV+ 0S V+ 0S /+ 0ST/+

0_{. 8}+ 0_.T8 ⁽¹²⁾

Finally, assuming equal channel length for all transistors, the transfer function of the amplifier is equal to:

(.)= ^Y^Z ^×^IJ^.*^=> ^{.K !"}

⎝

⎛K ⁼ ^{.% ] × ]}

#$%

^+,×%

⎠

⎞×aK _{^ PQ×% PQ}b

(13)

Where, c =^d_e^PQ

+, = ^!

^{af ]f}^{f .f} ^b]=

a .

. ] b _% (14)

Hence, equation (13) can be re-written as a single- pole transfer function.

(.)≈ ^Y^$

K ⁼ ^{.% ] × ]}

#$%

^+,× % (15)

So, for -3dB frequency we have:

hiVST≈ _jk.*^._Ll_.^!"a1 +^Y^$b ⁽¹⁶⁾

Moreover, the input referred noise current of M2 (defined by In3) and M5 (defined by In5) are written as follows (m defines the noise factor):

Figure 4. Active inductor implementation (a) Small signal model (b) Equivalent model

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4:V= 4:! (17) 4^j_{7n.o,n qV}

rrrrrrrrrrrrr = 4tum23V× ^j= 4tum23V× v^wjx^,^.*^y ^.e^z

wjx,.*y .ez{

j

= 4tum2_3V× ^! ^j ⁽¹⁸⁾

4^j_{7n.o,n qU}

rrrrrrrrrrrrr =4tum2_3U× | × |^j= 4tum ^! ×

|23}× |^j ⁽¹⁹)

Also, by performing same calculations for M2 and M4, one have:

4:j= 4:! (20)

4^j_{7n.o,n qj}

rrrrrrrrrrrrr = 4tum23j× | |^j= 4tum23j× v^wjx^,^.*^y ^.e^z

wjx,.*y .ez{

j

= 4tum2_3j× ^! ^j ⁽²¹⁾

4^j_{7n.o,n q}}

rrrrrrrrrrrrr =4tum23}× | |^j ₍₂₂₎ Although the thermal nose of M1, which is located in parallel with the PC of the input node, is negligible, Cpd produces thermal noise:

4^j_{7n.o,n q!}

rrrrrrrrrrrrr = tu0_HS (23)

By checking equations (18) and (21) out, one can see that by choosing low values for W1, not only the thermal referred noises of M3 and M2 are lessened, but also more Ohmic gain are achieved.

III. SIMULATION AND ANALYSIS The presented TIA is simulated using 90-nm CMOS technology (BSIM4) parameters. Figure (4) is the simulated frequency response, that shows 54.53dBΩ of gain and 1.7GHz of bandwidth. The circuit is biased using 1Volt supply, and consumes only 2 milli-Watt of power.

Moreover, the eye-diagrams are also simulated (see figure 5) using PRBS 2⁷-1 with 10µA, 100µ Ampere and 200µ Ampere input signals. The eyes are wide open, which indicate the proper quality of output signal.

Figure 4. Frequency Response

Additionally, Monte-Carlo simulation considering changes in dimensions of transistors over the frequency response is performed (see figure 6) for 200 runs.

Results show no unusual changes over the frequency response.

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(b)

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Figure 5. Eye diagram for (a) 100µA, (b) 200µA and (c) 10 µA random input signals

Figure 6. Monte-Carlo Analysis over transistor dimensions

Figure 7. Simulated Input Referred noise

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Additionally, the noise performance (input-referred) of the presented circuit is only 12.6pA/√Hz (see figure 7).

In addition, the layout of the proposed TIA is drawn (see figure 8), in which it occupies only 84µm² of area.

Figure 8. Layout

Finally, Table.I compares the performance parameters of the presented TIA with seven recently published TIAs. The main objective of the presented article is the noise performance beside power consumption. The presented TIA consumes the least power in the table, and provides one of the low noise performances (except in comparison with references [9]

and [18]). Nevertheless, as it essential to judge all aspects of circuits together, a Figure of Merit (FoM) is presented here (see equation (24)). Comparing according to the defined FoM, the overall performance of the presented circuit provides much better performance, except in comparison with [17] and [14].

These two references employ BiCMOS technology and not CMOS technology, and consume way more power than that of the presented paper (references [14] and [17], dissipate 75 times and 130 times more power than the presented paper, respectively).

~•€ =^{•‚ × ƒ. .}_'_z^ (^{Ω.•…†}₃ ) (24)

IV. CONCLUSIONS

Presented manuscript deals with a low-noise and low-power Transimpedance amplifier, which consumes only 2mW power and its input referred noise is equal to 12.6pA/√Hz, while provides 1.7GH bandwidth beside the Ohmic gain of 524.8Ω. The discussed TIA is simulated using 90nm CMOS technology in HSPICE using BSIM4, and the results clearly indicate its proper performance for 2.5Gbps applications.

TABLE I. PARAMETR COMPARISON

[4] [19] [18] [17] [16] [14] [9] This

Work Supply Voltage

(V) 1.8 1.5 1.5 3.3 1.8 3.3 1.8 1

Input referred noise

15

(pA/√Hz) 31.3

(pA/√Hz) 6.8

(pA/√Hz) 14.8

(pA/√Hz) 23

(pA/√Hz) - 9.33

(pA/√Hz) 12.6 (pA/√Hz) Gain

(dBΩ) 58 50.1 54 72 59 83.7 55-69 54.53

Power

Dissipation (W) 34.8m 7.5m 45m 261m 18m 150m 6m 2m

Cpd (fF) 300 250 - - 300 - - 250

Bandwidth

(GHz) 8.1 7 11.5 38.4 7.9 32.1 1 1.7

Technology 0.18µm

CMOS 0.13µm

CMOS 0.13µm CMOS

0.13µm SiGe BiCMOS

0.18µm CMOS

0.13µm SiGe BiCMOS

0.18µm

CMOS 90nm

CMOS FoM (^Ω.‡ˆ‰

Š‹) 184.8 299 128 585 425 3276 417 446

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