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STUDY OF LOW NOISE AMPLIFIER IN ULTRA WIDE BAND RANGEKumar Ajay Prasad1, Rishi Choubey2
1Research Scholar, Dept. of Electronics and Communication Engineering, SVN University, Sagar (M.P)
2Assistant Professor, Dept. of Electronics and Communication Engineering, SVN University, Sagar (M.P)
Abstract- An CMOS Low Noise Amplifier (LNA) is presented that works in Ultra Wide Band. In present scenario UWB standard is mostly used technology because of its low power consumption and extremely high data rate. For any UWB transceiver low noise amplifier is a important part. The LNA is a circuit that is responsible for providing sufficient gain to the signal at minimum distortion. In presented work to design the LNA at the transistor level CMOS 0.18u TSMC technology is used. Various components with various orientation are implemented for the proper gain over the frequency range of 3.1GHz to 10 GHz. Various parameters like voltage, power and noise are achieved with proper result. Agilent’s ADS tool has been used to design and simulate the whole circuit.
1 INTRODUCTION
1.1 Introduction of Low Noise Amplifier The widely use of telecom and wireless services system-on-chip (SoC) solutions is the major technology for the semiconductor industry. These wireless systems has two types first is front- end and second one is back-end section. The Front-end type technique analog signals is used in high radio frequency (RF) range and for the second one the back-end section processes analog and digital signals at low frequency range. The electromagnetic spectrum that is used for radio communications [1] uses Radio frequency (RF) for the frequency range.
That range is 100 KHz to 100 GHz.
However frequencies below 1 GHz are considered baseband frequencies while those greater are described as RF. The time is also a major factor for a designer to designe that meets the specifications.
High frequencies analog signals with a wide dynamic range uses RF circuit for process. RF components consist very small part of whole IC. This is the main reason that RF IC design involves a lot of tradeoffs in noise, power, gain and frequency in the “RF design hexagon”
shown in Figure below.
Figure 1: RF design hexagon
At least any two of six parameters are used in RF design hexagon to get come result. Low noise amplifiers are the mainstay of radio frequency communication receivers and by identifying the specifications we can estimate the overall noise performance of the RF Receivers. The radio signal received at the antenna is very weak.
Therefore, an amplifier with a high gain and good noise performance is needed to amplify this signal before it can be fed to other parts of the receiver. Such an amplifier is referred to as a LNA or Low Noise Amplifier. LNA is the first active amplification block in the receiving path as shown in Figure below.
Figure 2: RF receiver 1.2 LNA Architectures
In the designing of low noise amplifiers, the important goals are minimizing the noise Figure of the amplifier, producing higher gain, low power consumption and producing stable 50 ohm input impedance [8]. To achieve all these goals different LNA architectures are available. Low noise amplifier is the first stage in the receiver design. Since, the operating frequency is in RF frequency band of LNA, the circuit should be as simple as possible, especially for the RF frequency.
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Otherwise, the circuit noise becomes toohigh. Moreover, if the circuit is too complicated, the parasitic effects may distort the amplified signal. In this way, there are several fundamental low noise amplifier topologies for single ended narrow band low power low voltage design, like resistive termination common source, common gate, inductive degeneration common source, shunt series feedback common source, cascode inductor source degeneration.
1.3 Resistive termination common source
In resistive termination common source architecture, a resistor is added at the input side of the amplifier to get stable 50 ohm impedance, but will introduce some extra noise factor in the amplifier.
Resistor termination common source topology adds some noise to the LNA because of the resistor thermal noise. The resistive termination common source type design is shown in Figure.
Figure 3: Resistive termination common source
2 COMMON GATE
In this architecture, common gate or common base configuration is used as the input termination. Common gate topology, the gain is less than 10.0 dB with very low power consumption. The common gate architecture is shown in Figure.
Figure 4: Common gate
Shunt series feedback common source
The shunt series feedback common source topology, it is difficult to compare among gain, small noise figure and better input/output matching with very low power consumption. The shunt series feedback common source topology architecture is shown in Figure.
Figure 7: Shunt series feedback common source topology
2.1 Inductive degeneration common source
Inductive degeneration architecture is most commonly used in GaAs MESFET amplifiers. These amplifiers use inductive source or emitter degeneration to provide a real term in the impedance. Inductive degeneration common source topology satisfies the specification in very low power consumption, but the isolation is not good enough in comparison to the cascade inductor source degeneration topology. The inductive degeneration common source topology architecture is shown in Figure.
Figure 8: Inductive degeneration common source topology
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2.2 Proposed LNA DesignFigure 9: Proposed LNA design.
3 RESULTS
Noise Figure: Noise Figure is calculated 1.209 dB, 3.574dB and8.332dB at 4.5GHz, 5.5 GHz and 6.5 GHzrespectively.
Figure 10 Noise Figure
Voltage Gain: Voltage gain is calculated -39.968 dB (10.0 mV), - 43.591dB(6.6mV) and- 47.515dB (4.2mV) at 4.5GHz , 5.5 GHz and 6.5 GHz respectively.
Power Gain: Power gain is calculated -33.998 dB (19.9 mW), -38.678 dB (11.64mW) and -42.908 dB(7.15mW) at 4.5GHz, 5.5 GHz and 6.5 GHz respectively.
Figure 12 Power Gain 4 CONCLUSION
In this work, a capacitor cross- coupled with inductively source degenerated differential cascade LNA and capacitor cross-coupled without inductively source degenerated differential cascade LNA has been presented. The simulations of the circuit are carried out using UMC 0.18 µm CMOS process. The differential LNA design, we obtained a noise Figure, power consumption, voltage gain and power gain at different supply voltages 1.5 V and 1.8 V are reported here. In this design the gain depends on source inductance and Inter-stage inductor between input stage and cascoded stage boost gain and lower noise Figure. The performance results of simulations are reported. The proposed circuit is observed to consume low power in comparison to the existing circuits.
Table: 1 Parameter/
Frequency 4.5GHz 5.5GHz 6.5GHz NoiseFigure 1.209dB 3.574dB 8.332dB VoltageGain 10.0mV 6.6mV 4.2mV
PowerGain 19.9 mW 11.64mW 7.15mW
REFERENCES
1. Suraj Sharma et.al. presented a paper on
“Design of Low Noise Amplifier at 3- 10GHz for Ultra Wideband Receiver” in September 2013 in IJIRCCE journal.
2. Mostafa yargholi et.al. presented a paper on
“Resistive Feedback LNA With Dual Band
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Notch Filter for Suppressing WLAN Signals in UWB Receivers” in 2012 IEEE.
3. Rozi Rifin et.al presented a paper on “Design of an Inductor-Less LNA Using Resistive Feedback Topology for UWB Applications” in 2013 in RJASET Journal.
4. R.S.Sai Ram et.al. presented a paper on “ Analysis and Design of CMOS Cascode LNA for UWB Applications with Gain Enhancement and Out- Band Rejection Capability.” In July12 in IJERT.
5. Anuj Madan et.al presented a paper on “A 5 GHz 0.95 dB NF Highly Linear Cascode Floating-Body LNA in 180 nm SOI CMOS Technology” in IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, VOL.
22, NO. 4, APRIL 2012
6. Ravinder Kumar et. Al. presented a paper on
“DESIGN AND NOISE OPTIMIZATION OFRF LOW NOISE AMPLIFIER FOR IEEE STANDARD 802.11A WLAN” journal VLSICS Vol.3, No.2, April 2012.
7. Somit pandey presented a paper on “Analysis of Working of LNA in UWB Range” in AIJRFANS journal (13-212) in 2013.
8. Sohiful Anuar Zainol Murad et.al. presented a paper on “A Review of Low Noise Amplifiers Topologies for Wireless Sensor Network”
published in 2014 2nd International Conference on Electronic Design in journal Research Gate (375-379).
9. K. Yousef et.al. presented a paper on “A 2-16 GHz CMOS Current Reuse Cascaded Ultrawideband Low Noise Amplifier” year 2011 IEEE journal.
10. Xuan Chen, Quanyuan Feng and Shiyu Li,
“Design of a 2.5GHz Differential CMOS LNA,”
Progress In Electromagnetics Research Symposium, Cambridge, USA, pp. 203- 206, Jul. 2008.
11. L.R. Carley, G. Gielen, R.A. Rutenbar, and W.
Sansen. “ Synthesis tools for mixed- signal ICs: Progresson frontend and backend strategies”. In Design Automation Conference, DAC, pages 298–303, 1996.
12. A. Nunez-Aldana, N. Dhanwada, A. Doboli, S.
Ganesan, and R. Vemuri. “A Methodology For Behavioral Synthesis Of Analog Systems”. In Southwest Symposium on Mixed-Signal Design, pages162–167, 1999.
13. E.S. Ochotta, R.A. Rutenbar, and L.R. Carley.
“Synthesis of high-performance analog circuits in ASTRX/OBLX”. In IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, pages 273–
294, 1996.
14. G. Van der Plas et.al. “AMGIE-A synthesis environment for CMOS analog integrated circuits”. In IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, pages 1037–1058,2001.
15. R. Phelps, M. Krasnicki, R.A. Rutenbar, L.R.
Carley, and J.R. Hellums. “ANACONDA:
robust syn-thesis of analog circuits via stochastic pattern search”. In Proceedings of the IEEE Custom Integrated Circuits, pages 567–570, 1999.
16. R. A. Rutenbar and Georges G. E. Gielen and B. A. Antao. Computer-Aided Design of Analog Inte-grated Circuits and Systems.
John Wiley & Sons, 2002.
17. Derek K. Shaeffer, “1.5-V, 1.5-GHz CMOS
Low Noise Amplifier,” IEEE Journal of solid- state circuits, Vol. 32, No. 5, May 1997.
18. Somesh kumar and Dr. Ravi Kumar, “A 1.8V and 2GHz Inductively Degenerated CMOS Low Noise Amplifier,” International Journal of Electronics Communication and Computer Engineering, Vol. 2, Issue 4, pp. 150-154, july 2012.
19. Jung-Suk Goo, Hee-Tae Ahn, Donald J.
Ladwing, Zhiping Yu, Thomas H. Lee and Robert W. Dutton, “A noise optimization technique for integrated low noise amplifiers,”
IEEE J. Solid-State Circuits, vol. 37, no.8, pp. 994-1002, Aug. 2002.
20. Reza Molavi, Shahriar Mirabbasi and Majid Hashemi, “ A Wideband CMOS LNA Design Approach,” IEEE International Symposium on Circuits and Systems, vol. 5, pp. 5107 – 5110, May 2005.
21. Hong Qi and Zhang Jie, “A 1.5V Low Power CMOS LNA Design,” International Symposium on Microwave, Antenna, Propagation and EMC Technologies for Wireless Communications, pp. 1379 - 1382, Aug. 2007.
22. M. Muhamad and N.A Nordin, “An Area Efficient of 0.18µm LNA Using Power Constraint Method,” IEEE Mathematical/
Analytical Modeling and Computer Simulation (AMS), PP. 606 – 609, May 2010.
