To support multiple frequency bands with single hardware, simultaneous LNA is among the more preferred topologies. In this work, the impact of transformer-coupled input matching on simultaneous dual-band LNA is analyzed and verified. The main design issues in LNAs are the input matching for maximum power gain, low noise figure for better sensitivity and power consumption.
Some recent literature shows good input matching in a wideband spectrum with the help of inductively coupled input signal path using on-chip transformers. Since the load impedance of dual-band simultaneous LNAs is in the fourth order, the overall area of the LNA with the input matching components will be very expensive. If the input matching along with the transformer can be accommodated in simultaneous dual-band LNA, this can reduce the overall chip area.
Therefore this work focuses on an in-depth analysis of the simultaneous input-matched LNA along with the transformer. Basically [2] is single band architecture, he discussed the benefits of using input matching technique along with transformer. In [5] a simultaneous sub-1dB NF LNA which operates in both WLAN bands is presented.
This work focuses on analyzing the effect of transformer-coupled input matching in simultaneous dual-band LNAs.
Requirement of dual band LNA
CMOS LNA Fundamentals
- Introduction
- Input impedance
- Voltage Gain
- Inductive Source Degeneration
- Input impedance match
- Effective Trans-conductance of Matched Device
When the impedances are real, the conditions for power matching and resistance matching are equal. Figure 2.2 shows a circuit commonly used in the design of low-noise CMOS amplifiers. This circuit uses the input stage to provide a matching input and current gain at the resonant frequency.
A cache code is added to the input stage to soften the interaction between the input tank and output tank. The cache code also reduces the inverse gain through the amplifier and thus increases the stability of the circuit. Furthermore, the cache code reduces the effect of the Cgd of M1 by presenting a low impedance node at the drain of M1.
The output inductor, Ld, is designed to resonate at ωo with the node capacitance at the output. The input and output tanks can be adjusted to provide narrowband gain, but can also be offset from each other to provide a wider and flatter frequency response. We can calculate the following expressions for the voltage and power gain, assuming that the LNA in Figure 2.2 is input-matched.
Input impedance matching using inductive source generation is a very popular approach because matching at the source does not introduce additional noise (as in the case of using a shunt input resistor), and does not limit the value of gm (as in the case of the common-gate configuration). From equation (2), to achieve an Input match, the following condition must be satisfied. 3) Where is the transition frequency of the transistor. Once Ls is chosen to provide the input match, Lg can be chosen such that Zin is real and equal to equation (2) at the resonant frequency ωo.
To find the transconductance of the circuit in figure 2.3, first note that the input matching network forms a series RLC tank. The Q of the tank can be defined as. 5) Where is the resonant frequency defined in equation (4). It can be observed from equation (9) that the effective transconductance is independent of the gm of the device, and depends on CMOS process technology through the transition frequency.
Transformer Coupled Input Matching for Narrow Band LNA
- Target structure
- Input Matching Network
- Output stage
- Gain calculation
- Simulation and Results
Where Cgs is small so that a large series inductance is required at the gate of M1 to achieve the desired 50Ω impedance. To solve this problem, a capacitor (Cd) can be added between the gate and the source of M1. The input matching of a cascade stage with degeneration inductor is inherently narrowband due to the series RLC resonant circuit formed by Ls and (Cgs+cd) in this work the transformer is used to absorb this series RLC circuit in a broadband matching network.
In order to achieve high gain and good reverse isolation, a cascode stage is used in the amplifier core. Since the gate-source capacitance (Cgs) is small, an additional capacitance is added in parallel with Cgs to avoid a very high value of the source inductance that would otherwise be necessary to realize the real impedance. This shows a possibility of better input matching in a wide band and improved gain than the conventional circuit.
Therefore, this input matching technique is considered in dual-band simultaneous LNA to improve the input matching. The overall input impedance of the equivalent circuit, Zin, can be expressed as. 12) Parasitic resistance and transformer capacitance are not explicitly included in the equation. However, the frequency response characteristics of the Zin. are still well captured because parasitic RC has similar effects as Zt and C1. The final expression is shown at the bottom of the page as Eq. there is one zero at the origin, one complex zero, and two complex poles for practical RLC values that can be realized on the chip.
To achieve high gain under low voltage head, an inductor with a series resistance is adopted as the output load to implement a low-Q, tuned load to cover the desired bandwidth. A source follower buffer stage with a current source load is added at the output to drive an off-chip 50-Ω load under test. The proposed amplifier can be divided into two parts to derive its voltage gain: the input matching network and the cascode stage with an inductive load.
Since the output voltage at the drain of M2 is gm1 vgs1 Zload, the overall voltage gain of the amplifier shown in Figure 15) is Ain the voltage gain between Vs and Vin as defined in the figure.
MATLAB Simulation
CADENCE Simulation
Concurrent Dual-Band LNA
- Introduction
- Target structure
- Input matching
- Output stage
- Gain
- Simulations and Results
The simultaneous LNA architecture is shown in Figure 4.1 The source-degeneracy inductor (Ls) is added to realize the real 50Ω impedance for input matching. Figure.4.2 simplified equivalent circuit of the transformer-based input matching network Therefore the overall impedance of the circuit is. To achieve narrow-band gain in the bands of interest, the load-discharge network must exhibit high impedance only at those frequencies.
This can be done by adding a series LC branch in parallel to the parallel LC tank of a single-band LNA, as shown in figure. Each series LC branch introduces a zero into the gain transfer function of the LNA at its series resonant frequency. The frequencies of the zeros determine the frequency of the notches in the transfer function, which are used to significantly improve the receiver's image rejection.
Because the output voltage at the drain of M2 is gm1 vgs1 Zload, the overall voltage gain of the amplifier shown in Fig. 24) Ain is the voltage gain between Vs and Vgs1 as defined in Fig.
Matlab simulation
Conclusion
The broadband input stage is verified to be adequate in providing steady input matching and noise performance [9]. Simultaneous dual-band receiver architecture capable of operating simultaneously on two different frequency bands is introduced. It uses a new simultaneous dual-band LNA, combined with an extensive frequency conversion scheme to reject the out-of-band signals.
The effectiveness of the proposed methodology is demonstrated by measurement results of a CMOS implementation of the integrated simultaneous dual-band LNA that achieves a superior S11, and power dissipation.
Broad-Band Input Matching Technique for Concurrent LNA
- Introduction
- Target structure
- Input stage
- Output stage
- Simulation and results
- Tunable Dual-band LNA
- Conclusion
The overall input impedance of the equivalent circuit, Zin, can be expressed as. 29) The parasitic resistance and capacitance of the transformer are not explicitly stated in Eq. Nevertheless, the frequency-response characteristics of Zin. is still well captured because the parasitic RC has similar effects to Zt and C1. The input impedance of the amplifier in Fig. 1 can then be derived based on Eq. 28) by replacing Zt with the series RLC circuit looking into the gate of M1. Equation (28) shows that Zin has a zero at the origin, a complex zero and two complex poles for the practical RLC values that can be realized on chip.
For the target bandwidth of 2–7 GHz, the complex zero is set at 4 GHz and the two complex poles are set at 2.5 and 7 GHz, as shown in the figure. For the design limit, the input matching bandwidth is designed from 2–6 GHz. Since the output voltage at the drain of M2 is gm1.vgs1.Zload, the total voltage gain of the amplifier shown in Figure 32) is Ain the voltage gain between vs and vgs1 as defined in the figure.
Where the bands of LNA can be tuned to the required frequencies by switching the output network capabilities. Where we can see that fading in each band is limited by the input matching bandwidth and the number of bands. As the number of bands in the output network increases, the fading in each band will decrease.
The broadband input stage has been verified to be adequate in providing steady input matching and noise performance. Varying the capacitance in the output circuit provides a wide tuning range with good performance consistency. Implemented in 0.18-µm CMOS technology, the results show that the proposed LNA paves the way to a new generation of low-power UWB applications.
As the number bands in the output network increase, the fading in each band will be reduced.
Conclusion and Future Work
Conclusion
Future Work
