Prateek Kumar Sharma

80 5.6 (a) Proposed baseband TIA using a second-order baseband NC scheme. e) Design of the blocks/components of the proposed first receiver mixer. 5.22 (a) Block diagram and (b) implementation of 4-phase clock generation. c) Dynamic power consumption of the receiver at 1 GHz.

Introduction

Full-duplex system

A cancellation signal can be generated by tapping a copy of the transmission signal and adjusting its amplitude, delay and phase. In narrowband systems, the effect of group delay can be approximated by phase delay.

Full-duplex requirements

Full-duplex link budget

The purpose of the link budget is to divide the total SI cancellation (SIC) required between the three cancellation stages: RF, analog and digital. Total SI cancellation 97 dB To suppress SI below noise floor RF SI cancellation 27 dB Calculated from (1.7).

Figure 1.9: Power level of SI signal after different cancellation stages.

Objective of the thesis

Low noise level (Pnoise) -91 dBm Calculated from NF and bandwidth Isolation 20 dB Antenna isolation and return loss.

Contribution of the thesis

The proposed balun is based on 2-port N-band filters and exploits their built-in phase shift property. The proposed duplexer uses two 2-port N-band filters with built-in phase shift [26] to form a balun that rejects transmitter leakage to the receiver.

Review of transmitter leakage canceling circuits

In configuration A, the transmission signal is applied to the center of the primary winding of the hybrid transformer, as shown in Fig. In this duplexer, the oscillation of the transmit signal appears as a common mode at the inputs of the differential receiver.

Figure 2.1: Various configurations of transformer-based duplexers.

N-path circulator [29]

The limitations on the antenna impedance variation and frequency dependence remain due to the limited tunability. In [6], a calibration loop is implemented to detect the TX leakage generated due to an unbalance in the duplexer and correct the balance network impedance to detect antenna impedance variation.

Transformer based duplexer to transformer-less duplexer

The signal received from the antenna enters the main winding of the transformer from one of its ends. Under perfect balance conditions, the transmit signal appears with equal magnitude and phase (−90◦ with respect to the signal at the TX port) at the ANT and BAL ports.

N-path BPF

The characteristic impedance of the transmission lines is optimized to achieve the input match at the receiver port. Another interesting property of the 2-port N-path BPF is the phase non-reciprocity (∠H216=∠H12), as shown in Figure 2.

Proposed N-path balun BPF

Single-to-Differential (SD) mode of operation

2.6(b) shows the simulated SD transfer functions of the Balun overlaid with the corresponding analytical expression. 2.6(b), the difference between the estimated in-band SD voltage gain and the simulated voltage gain is <0.2 dB.

Figure 2.6: (a) Computation of Single-to-Differential (SD) voltage gain in the Balun BPF

Differential-to-Single (DS) mode of operation

The analytical expression in (2.9) was validated by the design and simulation of a Balun using ideal elements. 2.7(b), the difference between the estimated in-band voltage gain and the simulated voltage gain is <0.3 dB.

Simulation results

Phase imbalance is the deviation of the phase difference between the outputs from 180◦ and the amplitude imbalance is the difference in magnitude of the two outputs. It has the inherent property of impedance transformation. The ratio between secondary and primary impedance is 2:1. It is used in electrical balance-based duplexers that provide good TX-to-RX isolation.

Figure 2.8: (a) Layout of the Balun in CMOS 65 nm technology. Schematic ( −− ) and post-layout (—) results:

Analysis of the proposed duplexer

During the Transmitting Mode

One of the disadvantages of the series coupling capacitor is that it reduces the gain of the ANT-RX. The TX-ANT insertion loss (IL) can be derived as 2.11), where Z0 is the characteristic impedance of the transmission line, Rs is the impedance of the TX (and RX) ports, Zlis the total impedance (Rsk(jωC1. c+ZN path)) at the ANT port, Ccis is the coupling capacitor and ZN path is the input impedance of the BPF N-way with short-circuit output.

During the Receiving Mode

Results of the scheme (−−) and subsequent layout (—) of the duplexer: (b) TX-ANT insertion loss and TX-RX isolation (c) ANT-RX insertion loss (d) OB filtering during receive mode (e) NF during receive mode (f) IB-IIP3 and OB-IIP3 during receive mode.

CMOS implementation and simulations

The ANT-to-RX path of the duplexer is (clock) tunable from 450 MHz to 650 MHz without adjusting the transmission lines (or changing the LC values). Any mismatch in amplitude, delay or phase will result in an incomplete cancellation of the SI.

Figure 3.1: Block diagram of a typical FD transceiver including an SI canceller. The canceller path should provide the amplitude, phase, and group delay tunability.

Review of transmitter echo canceling circuits

The effect of Rs on the magnitude of the transfer function is shown in Figure. The transconductance Gm is used to shift the center frequency of the filter, as shown in Figure 2.

Figure 3.4: Magnitude and phase response of N path G m − C canceller filter [12].

Passive vector modulator [13]

The implementation of the passive vector modulator downmixer [13] is similar to the transconductance vector modulator [41] with the only difference; it only has switches and no gm steps. The number of constellation points depends on the number of slices used in the vector modulator.

Adaptive double cancellation [14]

The minimum amplitude is obtained when half of the disks are set 180 out of phase to the other half. The cancellation is measured for each vector modulator setting, and an algorithm based on power minimization is used to find the amount of cancellation.

Proposed full-duplex receiver

Vector modulator

Resolution

The operation of the variable attenuation N-path sampling mixer can be explained with the help of the single path shown in Fig. Q-cancellation is.

Figure 3.11: Sharing one capacitor bank among four-paths. In an eight-path canceller, two capacitor banks are sufficient.

Noise canceling TIA

Transistor-level schematics of the (b) first and (c) second stages of the TIA. d) The dimensions of the transistors used in this work.

Other blocks

Receiver analysis

Input impedance
Gain
Noise

Noise canceling condition
Noise Factor

Linearity

3.18(a) shows a comparison of the simulated and analytical (3.14) voltage gain of the receiver for different gma/gm2 ratios at fRF = 500 MHz. Letvn,s2 = 4kT Rs,v2n,sw= 4kT Rsw,v2n,sh = 4kT Rshandvn,f2 = 4kT γRF represents the mean square thermal noise voltage densities of the resistors Rs,Rsw,Rsh and RF respectively.

Figure 3.16: (a) Equivalent LTI model of N-path mixer-first receivers. (b) Input impedance of the TIA per path.

Implementation details

The range of the attenuation capacitance values (Cmax to Cmin) depends mainly on the size of the switches. The size of the switches in the capacitor bank is chosen based on the trade-off between the quality factor (Q) and the capacitance range.

Measurement results and discussion

When the SI canceller is OFF

As the size of the VM switch increases, the OFF capacitance of the switch increases, leading to a reduction in the VM's dynamic range (the ratio of maximum to minimum attenuation). Therefore, there is a trade-off between the maximum operating frequency of the VM and the dynamic range of the VM.

Figure 3.21: Measurement results in HD mode: (a) variation of gain and NF with LO frequency, and (b) variation of P1dB, IB-IIP3 and OB-IIP3 with LO frequency.

When the SI canceller is ON

The phase of the canceller signal refers to the output signal for the same I-code and Q-code. The receiver gain is measured relative to the desired signal in the presence of SI.

Figure 3.23: (a) Normalized output versus varactor tuning voltage, and (b) a few constellation points obtained in measurements.

Introduction

IIP3 and NF systems are mostly limited by the receive path rather than the cancellation path. To improve the performance of the proposed FD receiver, the baseband stage of the first mixer receiver should have high IIP3 and low NF.

Input impedance of a mixer-first receivers

Regimes of operation

Noise-limited regime

Variation of NF with RF for different input referenced noise voltage of transconductor (b) in a 4-way mixer-first receiver, and (c) in an 8-way mixer-first receiver (Solid lines indicate simulation, while dashed lines indicate ( 4.5)). from the TIA to the overall receiver noise. The NF of the receiver in this noise-limited regime depends on v2n,gm and RF.

Linearity limited regime

4.4(c), one can conclude that the NF of the receiver can be brought closer to the NF of the mixer alone in a linearity-limited regime. Thus, the IB-IIP3 of a receiver operating in the linearity-limited regime is smaller than the IB-IIP3 of a receiver operating in the noise-limited regime.

Figure 4.5: Variation of NF, gain and IB-IIP3 of the receiver (implemented with inverter based TIA) with feedback resistance R F in (a) a 4-path mixer-first receiver, and (b) in an 8-path mixer-first receiver.

Design Examples and simulation results

Noise-limited regime

4.5(b) shows the variation of simulated NF, gain and IB-IIP3 with RF in the first 4- and 8-path mixer receivers respectively. 4.5, it can also be noted that the values of gain and IIP3 can be adjusted by changing the value of RF in the noise-limited mode.

Linearity-limited regime

In the linearity-limited regime, the noise contribution of the OTA can be reduced by increasing the gm value. The power consumption of a receiver operating in the linearity-limited regime is higher than a receiver operating in the noise-limited regime.

Design for high SFDR

The input impedance of the first N-receiver path mixer at the center frequency is given by [52]. The static power consumption of the receiver depends on the bias current of the opamp Ib and is given by.

Figure 5.1: (a) Typical N-path mixer-first receiver with a shunt feedback TIA. (b) Design constraints on the opamp to achieve required specifications.

Review of N-path mixer-first receivers for enhanced linearity

Mixer-first receiver with baseband noise-canceling circuit [85]
Mixer-first receiver driving an impedance with 40 dB/decade roll-off [72]
Mixer-first receiver with baseband capacitive positive feedback [65]
Mixer-first receiver with baseband shunt notch [69]

A second-order passive mixer receiver is presented in [72] to improve channel selectivity, linearity and noise figure in the presence of OB jammers. An improved first mixer receiver with positive capacitive feedback is presented in [65] to obtain a steeper filter rolloff and enhanced linearity while keeping NF low.

Figure 5.2: Mixer-first receiver with baseband noise-canceling circuit [85].

Baseband TIA

OTA based TIA
Proposed second-order TIA
Theoretical analysis
Limitation of the TIA under the input-matching constraint

The input impedance of the proposed TIA can be adjusted independently by adjusting only the gm1 value. The NF of the proposed TIA (and thus the receiver) is dominated by the NF of the auxiliary transceiver.

Figure 5.6: (a) Proposed baseband TIA using a second-order baseband NC scheme. Illustration of (b) input- input-match and OB-IIP3, (c) NF, and (d) IB-IIP3 using the proposed TIA

Receiver

Input Impedance
Gain
Noise

Noise-canceling condition
Noise Factor

Linearity
Static Power

The noise factor equation (5.35) is verified by simulations of the receiver for various input noise voltages (vn,gma) of gma. 3The IB-IIP3 and OB-IIP3 of the receiver (including only switches nonlinearity) are calculated in Appendix B using MOSFET square-law model.

Figure 5.11: (a) Equivalent LTI model of an N-path mixer-first receiver. (b) Input impedance of the TIA per path.

Design Procedure and CMOS Implementation

Four-phase clock generation

The output buffers consume the majority (57%) of the total dynamic power as they drive the wide-width mixer switches. The input buffers that provide broadband impedance matching consume 31.5 mW of power at 2 GHz (ie, a LO frequency of 1 GHz).

Mixer switches

The clock signals are generated using an on-chip frequency divider and a set of combinational digital circuits. An off-chip differential clock signal at 2×LO frequency is used as an input to the clock generator.

Baseband TIA

Measurement Results

Figure-of-Merits (FOMs)

In the case of OB performance, the size (and thus resistance) of the mixer switches determines the dynamic current consumption and OB-IIP3 at far offset frequencies. Therefore, the FOM is modified to include OB-IIP3 at far offset frequencies and the dynamic power consumption.

Tab. I shows a comparison of IBFOM, OBFOM and ACFOM of this work with the state-of-the-art mixer-first receivers

Conclusion

Future scope

Nonlinear op-amp and OTA models are considered for the IIP3 rating of the receiver. The following subsections discuss the trade-offs between input matching, linearity, noise, and power for opamp- and OTA-based TIAs.

Dependence of Linearity on Input-match

In other words, if the IIP3 of the opamp is 0 dBm in open circuit, more than 8.2 dBm of IIP3 can never be achieved for an input-matched receiver. A.2(a) shows a comparison between the simulated and analytically normalized IIP3 (A.5) of the receiver for different RB values.

Degree of freedom for noise figure and power

A.1(b), the noise figure of the receiver is mainly determined by the noise voltage of the op amp.

OTA based TIA

Degree of freedom for Linearity

The receiver's IIP3 is normalized with respect to the IIP3 obtained in the open-loop case from (A.8) and (A.9). A.3(a) shows a comparison between simulated and analytical (5) normalized IIP3 of the receiver for different RF values.

Figure A.3: Comparison of simulated and analytical (a) Normalized IIP3 and (b) NF of the receiver using OTA based TIA.

Dependence of noise figure and power on input-match

Challenges in breaking the tradeoffs

IIP3 of a mixer-first receiver with a shunt-feedback TIA

The forward TIA network is replaced by its equivalent Thevenin network, as shown in Fig. The opamp is assumed to have a third-order nonlinear transfer characteristic, as shown in Fig.

Figure B.2: Theoretical (a) IB-IIP3 and (b) OB-IIP3 of the receiver (considering only the non-linearity of switches).

Computing α 1 and α 3 using the square-law model

Simplified expressions of IB-IIP3 and OB-IIP3

Global mobile data traffic

Transmit and Receive signal in (a)Time-division-duplexing (TDD), (b)Frequency-division-

Self interference in FD radios

SI canceller architectures with different locations of TX tapping

SI canceller architectures with different injecting points

SI cancellation in digital domain

SI cancellation in both RF and digital domain

Power level of SI signal after different cancellation stages

Complete block diagram of the FD transceiver (The proposed blocks are depicted with

Various configurations of transformer-based duplexers

Implementation of N-path based circulator [29]

Common-mode and differential responses during the DS operation. Dashed lines are

Block diagram of a typical FD transceiver including an SI canceller. The canceller path

Effect of phase mismatch between the SI and the canceller signals on SIC

General considerations

Nauta, “Unified Frequency Domain Analysis of Passive Series Discontinuous-RC Mixers and Samplers,” IEEE Trans. Nauta, "Unified Frequency-Domain Analysis of Switched-Series-RC Passive Mixers and Samplers," IEEE Trans.