Design Procedure and CMOS Implementation

Zin, NF, Gain, IB-IIP3 OB-IIP3, BW,Pdc

Start

Feasible?

according toZin

Setgm1=_R¹_B Eq.4 NO

YES

according to Gain SetR1 Eq. 25

according to NF Setgma Eq. 37

according to NC Setgm2 Eq. 30

for transconductors Choosegm/ID

Get bias currents ofgm1, gm2, gma

Total current

< Pdc/Vdd? YES

Linearization

based onQ, BW SetR2, C1, C2

on IB-IIP3 Getg^′′_m2based

YES Enough margin

inPdc? YES

Choose topologies

Stop Output:gm1,gm2, gma,R1,R2,C1,C2,

Rsw, bias currents required?

andωz

dynamic power on OB-IIP3 and SetRswbased

ofgm1, gm2, gma

Figure 5.20: Typical design flow of the proposed receiver.

5.5 Design Procedure and CMOS Implementation

The following input specifications are considered in this design flow: Z_in(orR_s), NF, IB-IIP3, OB- IIP3, gain, bandwidth (BW), number of paths (N), and power consumption (P_dc). Fig. 5.20 shows a flow-chart of the typical design procedure. The first step of the design procedure is to check the design feasibility. Probable checks include very smallP_dc, very small NF, very high IIP3, very high Gain-BW product, etc. The size of the mixer switch should be chosen based on the OB-IIP3 requirement and the dynamic power consumption specification. The transconductance of the Rauch filter (gm1) should be chosen based on the input-match requirement. One can estimate thegma required to achieve the desired NF using (5.37). Using the noise-canceling condition (5.30) and thegmavalue, one can estimate the required gm2 value. The bias currents of all the three transconductors can be obtained based on the choseng_m/I_D values. We need to check the total power consumption and adjust the bias currents according to the given specification (P_dc). The values of remaining passive componentsR₂,C₁ andC₂ can be obtained based on the BW specification and (5.11)-(5.13). One can roughly calculate theg⁰⁰_m2 required to achieve the required IB-IIP3 and decide weather a linearization technique is necessary or not forgm2. The complete block diagram of the implemented chip is shown in Fig. 5.21. The design

−

v_b ^P¹

v_b ^P³

v_b ^P²

v_b P4

gm2

gma

gm1

gm2

gma

gm1 by

v_XI v_{Y I}

v_XQ v_{Y Q} ioutQ

ioutI

R_s

g_ma = 20 m℧

g_m1 = 3 m℧ g_m2 = 1 m℧

vb = 1 V

R₁ = 2.4 kΩ R₂ = 200 Ω

C₁ = 1 pF C₂ = 50 pF C_c = 40 pF

Chip

V_s

divide CLK

C_c

P1−P4

Figure 5.21: Complete block diagram of the implemented mixer-first receiver.

Input Buffers

S1 S2

B A

C QB

D Q DB

D flip-flop

H S6

A H

ClkClkb ^D

DB Q

QB D

DB Q

C CB CB C

E F

G H DIV-BY-2

30%

13%

57%

AND Logic

(b) (c)

(a)

31.5 mW

14 mW AND+buffers Input stage

divider

62.5 mW 108 mW at 1 GHz

Figure 5.22: (a) Block diagram and (b) implementation of 4-phase clock generation. (c) Dynamic power consumption of the receiver at 1 GHz.

and implementation details of each block are given below.

5.5 Design Procedure and CMOS Implementation

5.5.1 Four-phase clock generation

The mixer switches are driven by 4-phase non-overlapping 25% duty-cycle clocks. The clock signals are generated using an on-chip frequency divider and a set of combinational digital circuits.

Fig. 5.22(a) shows the block diagram the 4-phase clock generator. An off-chip differential clock signal at 2×LO frequency is used as an input to the clock generator. Fig. 5.22(b) shows the circuit diagrams of the D-latch and AND gate. The clock generation circuitry consumes 108 mW of power at 1 GHz.

Fig. 5.22(c) shows the distribution of the dynamic power consumption of the receiver. The output buffers consume a major portion (57%) of the of the total dynamic power as they drive mixer switches with large width. The input buffers, which provide the broadband impedance matching, consume 31.5 mW of power at 2 GHz (i.e., 1 GHz LO frequency).

5.5.2 Mixer switches

In the current four-phase mixer implementation, NMOS transistors are used as switches. The mixer switches are dc coupled to the baseband TIA. This dc coupling forces the potential at source and drain terminals of switches to be ≈V_dd/2. This dc voltage reduces the overdrive voltage (V_OD) of switches which results in poor OB-IIP3. Using the square law model of the MOSFET, the OB-IIP3 of the mixer-first receiver can be shown to be as follows [86]⁴

OB−IIP3 = s

8 3

(1 +ρ)⁴

ρ³ V_OD² , (5.49)

where ρ = R_sw/R_s, R_sw is the switch resistance, and V_OD= V_GS−V_th is the overdrive voltage of the switch. To improve the OB-IIP3, the mixer switches are biased using capacitive coupling at their gates. In the current implementation, V_OD is equal to ≈1.2 V. From (5.49), one has to choose small Rsw for a large OB-IIP3. A smallerRsw requires a larger width for switches which results in a greater dynamic power consumption. In the current implementation, the switches are sized to have an ON resistance of 5 Ω. The corresponding NMOS transistor dimension is 150µm/180nm. Using (5.49), the estimated OB-IIP3 of the receiver is +47 dBm. Fig. 2 of Appendix B shows the theoretical OB-IIP3 of the receiver for various switch resistances.

− +

vin

gm1 gma ^{V dd}^aux gm2

vin

V dda V dda

vin

vin+

vb1

vin−

vin+

v_in−

vout

vout V dda

RL2,p

RL1,p

RL1,n

RL2,n

5 pF

floating

battery error

amplifier RL

vout

vout 460u

100u 1u 92u

1u 0.2 mA

20u 1u

20u 1u 92u 1u

30u 0.18u

20u 0.18u

10u 0.18u

0.2 mA 0.1 mA

(a) (b) (c)

Figure 5.23: Circuit implementations ofgm1,gma andgm2.

5.5.3 Baseband TIA

The baseband TIA is designed to have a bandwidth of ≈ 20 MHz. The zero in the TIA input impedance is at≈ 40 MHz. Fig. 5.23 shows the schematic diagrams of the three transconductorsgm1, gma, andgm2. CMOS inverter-based transconductor topologies are used for better linearity and NF.

The component values and transistor sizing used in the current implementation are shown in Fig. 5.23.

From the input matching requirement, we need agm1 = 3 mf. The noise and distortion due togm1

are canceled by the NC scheme. Therefore, theg_m1can be optimized for smallest power consumption.

A current biased differential inverter based transconductor topology, shown in Fig. 5.23(a), is chosen forg_m1. The transistors are sized to have an output common mode voltage ofV_DD/2. The transistors are operating at ag_m/I_D of 15.

The auxiliary transconductorgma limits the overall noise performance of the receiver. We wanted to test the receiver without the auxiliary path also. Accordingly, enable switches are added in the supply and ground paths of the transconductor. The circuit level implementation of gma is shown in Fig. 5.23(b). The required gma value is 20 mf. Each inverter consumes 1.8 mA of current resulting in a gm/ID of ≈5.55 for each transistor.

The implementation of the second transconductor g_m2 is critical for the receiver linearity. [87]

discusses various techniques to improve the linearity of a transconductor. In this work, inverters with resistive source degeneration in both NMOS and PMOS are used for the implementation ofg_m2. Further, a floating battery-based linearization technique [88] is used to improve the linearity of g_m2. The source voltages of PMOS and NMOS transistors of the degenerated inverter have fundamental

4The OB-IIP3 of the receiver (considering non-linearity of the switches) is also discussed in Appendix B.

Dalam dokumen Prateek Kumar Sharma (Halaman 123-127)