PDF ELECTRONIC PROPERTIES AND RELIABILITY OF THE SiO2/SiC INTERFACE

Obtained interface trap densities in the upper half of the 4H-SiC band gap. after various post-oxidation annealing. The thesis focused on the electrical properties and reliability of the oxide and its interfaces with silicon carbide.

Semiconductor Properties

The polytypes can be constructed by stacking a close-packed, planar, hexagonal array of the Si-C tetrahedra at the corners [Figure 1.1(b)]. Such distinctive kinetics may be related to the complex oxidation process that requires the release of carbon.

Table 1.1: Key constants of 4H-SiC and silicon. 1, 2,3,4

SiC Device Physics

Critical field and blocking voltage

In the case of a one-sided compound (eg n-dopingp-doping), the reverse bias leads to the depletion of carriers almost exclusively in the low-doped region. In the OFF state, the PN junction formed by the operating region and the base supports the positive drain voltage, there is no current.

SiC power MOSFET

In this section, two of the main components of the total specific ON resistance are discussed: the power specific resistance and the channel specific resistance. Again, the values of LandP must be optimized in the design and ξox is limited by the reliability of the oxide.

Figure 1.6: Achievable speciﬁc ON resistance as a function of the designed blocking voltage for Si and 4H-SiC devices

Technology status and challenges

SiC wafer quality

Although SiC substrates have only been commercially available since the last decade, tremendous progress has been made with regard to the quality and the size of the wafers. One outstanding issue for material developers is therefore to continue to improve the techniques for further reducing the defect density to optimize device properties and reliability.

The gate oxide

As discussed earlier, in the OFF state of a DMOSFET, an electric field is present in the gate oxide and this can limit the achievable blocking voltages. In the ON state, a bias voltage is applied to the gate to form an inversion layer in the base region.

The SiO 2 /SiC interface

A third C-related level in the upper part of the gap is attributed to 3C-SiC inclusions on the SiO2/4H-SiC surface. The unsaturated carbon in these stable configurations yields one level in the upper part of the 4H-SiC band gap and one near the edge of the valence band.

Figure 1.7: Schematic of the density of traps at the oxide/semiconductor interface. The relative positions of the conduction (E c ) and valence band edges (E v ) are indicated

Drift Conduction and Breakdown

There are different displacement tracking regimes, 2,3,4,5,6 as illustrated in Figure 2.1 where the net velocity is plotted as a function of the electric field. From equation (2.1), this implies a linear dependence between the net velocity of the carrier and the electric field.

Charge Transport and Trapping in the Oxide

Band and hopping conduction in amorphous dielectrics
Transport in SiO 2
Trap charging kinetics
SiO 2 bulk trapping and interface state generation

Changes in the lattice lead to modulation of the local atomic potentials and the relative position of the band edges across the solid. However, in the case of SiC, this can be challenging due to the large times required for charge emission from deep interface states, as discussed in Section 2.4.4.

Figure 2.3: ”Alpine” model of the inﬂuence of disorder upon the band structure of a dielectric

Injection Mechanisms

Quantum tunneling
Thermionic emission
Frenkel-Poole emission
Fowler-Nordheim tunneling
Internal photoemission
Radiation-induced carriers

We can see that in both cases the wave function of the carriers extends into the oxide (Tt[5 ˚A]1%). When the conduction band of the oxide is bent, it crosses the energy level corresponding to the level of the free carriers in the emitter.

Figure 2.7: Tunneling probabilities from the conduction band of Si and 4H-SiC as a function of the depth in SiO 2 calculated from Eq.(2.19) using m ∗ = 0.5 m.

MOS Capacitance

Nature of charges
Interface population
Small signal capacitance
Capacitance-Voltage measurements

A graph of the total charge in the semiconductor as a function of the gate bias is shown in Figure 2.17(b). Low frequency (LF) and high frequency (HF) limits of the hi-lo CV techniques are indicated.

Figure 2.16: (a) Four categories of oxide charges in the MOS system. (b) Energy levels at the oxide/semiconductor interface

GROWTH KINETICS ON SiC

Motivation

These results have additional significance in light of the current interest in the SiO2/4H-SiC system. The results presented here enable a direct examination of the dependence of the electrical properties on the growth rate at a given temperature (1150 ◦C).

Figure 3.1: SiO 2 thickness on the (0001) Si-face of 4H-SiC as a function of time for dry oxidation performed at 1150 ◦ in ﬂowing oxygen (1 atm)

Growth Kinetics

This derivation takes into account the out-diffusion of the CO gas which is a byproduct not present in Si oxidation.10 The new linear rate constant is. The temperature dependence of the growth kinetics arises from the diffusion coefficients and from the reaction rate constants, all of which describe thermally activated processes.

Table 3.1: Equilibrium concentration of O 2 in the oxide (10 16 cm −3 ) at 1150 ◦ C.

Experiments

Results and Discussion

Initial oxidation
Extraction of growth parameters
Electrical properties of the interface

As mentioned above, the pressure dependence of the oxidation kinetics is reflected in the linear and parabolic rate constants. This is, of course, if the dependence of the rate constants on the pressure is linear.

Figure 3.3: The ﬁt of the linear-parabolic relationship to oxidation data in dry oxygen at 1 atm on the (0001) Si-face at 1150 ◦ C

Summary

The flatband voltage stability of SiO2/SiC MOS capacitors upon electron injection can be improved by introducing nitrogen into a thermal gate oxide. The role of nitrogen in this effect, and how it can be linked to the passivation of interface defects, is discussed next.

Motivation

In this chapter, it is shown to originate from the suppression of negative charge build-up in interfacial states during injection. In this chapter, it is shown that the origin of the nitrogen-induced reliability improvement lies in the suppression of interface state generation by electron injection into NO-annealed oxides.

Experiment

The energy values refer to the respective band shifts between the metal, insulator and semiconductor. Hysteresis of high-frequency CV curves was used to detect energetically deep interface states and slow boundary states.

Results

This trapping cross section is close to that found for the unpassivated samples, suggesting that trapping still occurs in the bulk of the oxide, but not at the SiO2/SiC interface. The CV curve shift is caused by the negative charge trapped in the bulk of the oxide.

Figure 4.2: Eﬀective density of trapped charge, deduced from the ﬂatband voltage shift, as a function of the injected electron density

Discussion

There is also a saturation of trapped charge for doses above 2 × 1016 cm−2, indicating the absence of interface state accumulation. In this case, the flowing electrons induce the release of the passivating species, leaving the dangling bonds as "new" interface states.25 Here we observe the degradation of the oxidized, unpassivated SiO2/SiC interface.

Table 4.1: Some defects predicted by theory to relax upon electron capture and their ability to be passivated by nitrogen

Summary

INCREASED OXIDE HOLE DENSITY ASSOCIATED WITH THE INCORPORATION OF NITROGEN AT THE SiO2/SiC INTERFACE. Incorporation of nitrogen into the SiO2/SiC interface via high-temperature NO annealing leads to the passivation of electrically active interface defects, leading to improved inversion mobility in the semiconductor.

Motivation

The content of this chapter has been accepted for publication in the Journal of Applied Physics.1. Charge annealing results in the neutralization of trapped charge and the removal of generated (near-) interface states.

Experimental and Theoretical Methods

Here, a low intensity UV light (< 3.5 eV) was used to generate an inversion layer, source of tunnel holes, in the negatively biased n-type substrates. A plane wave energy cutoff of 396 eV and the Γ point in the Brillouin zone were used for the calculations.

Figure 5.1: Eﬀective charge density trapped upon carrier injection by three diﬀerent techniques; (a) 10 keV X-rays under positive gate bias, ξ ox 1.5 MV/cm, (b) 10 eV VUV photons under positive gate bias, ξ ox 1.5 MV/cm, and (c) Fowler-Nordheim tunneling

Results

Hole Injection
Charge Annealing

To understand the nature of the excess positive charge in nitrated samples, charge annealing was performed after injection. Furthermore, the annealing rate of the generated switching states appears to match that of the positively trapped charge [Figure 5.3(b)].

Figure 5.2: Evolution of the photo-CV hysteresis of a NO-annealed n-type sample. A low intensity UV pulse was applied at -10 V, prior to the sweep towards accumulation, in order to form an inversion layer and empty deep/slow states.

Discussion

This can be seen in Figure 5.2, where the width and position of the hysteresis after electron-induced annealing are very close to their values before injection. After capturing a hole, it becomes empty and its energy level moves down towards the edge of the SiO2 valence band, just like that of the doubly occupied state.

Figure 5.4: Conﬁgurations resulting from N and NO incorporation in SiO 2 . The energy of the corresponding levels, are noted in eV

Summary

DENSITY OF EDGE STATES, ELECTRON TRAPS AND HOLE TRAPS AS A FUNCTION OF NITROGEN CONTENT IN SiO2 ON SiC. This makes it possible to compare the evolution of the density of boundary states, electron trapping and hole trapping as a function of nitrogen content.

Motivation

Nitriding of the SiO2/SiC interface provides resistance to electron injection (Chapter IV) as well as an increase in hole trap density (Chapter V). Trap densities in the gate dielectric of metal oxide semiconductor (MOS) capacitors are characterized as a function of the amount of nitrogen embedded in SiO2.

Experiments

The change in flatband voltage upon injection ΔVf b was monitored by the shift of the high-frequency CV curve measured against flatband capacitance and was renormalized to the shift that a 50 nm oxide would produce, so that all samples can be directly compared. The g value, characteristic of the ESR signal, was calculated from the applied field at resonance.14.

Figure 6.1: Schematic of the electrical connections of the designed automated injection setup

Results and Discussion

Kinetics of the nitrogen uptake
Impact of temperature and slow re-oxidation
Progressive reduction of the interface state density
Suppression of electron-induced interface state generation
Increase in hole trap density

The curve is ﬁtted by Eq.(6.3), the resulting values of the parameters are listed. It should be noted that the treatment of the samples was different in the two experiments.

Figure 6.2: SIMS proﬁles for the samples annealed in NO for 7.5 min, 30 min and 120 min.

Summary

In the case of Si, nitrogen can be removed from the interface by a reoxidation process to reduce NBTI without destroying the N-related enhanced oxide properties. However, in the case of SiC, the presence of nitrogen at the interface is necessary to passivate or remove defects and to increase the channel mobility of oxide-based devices.

Motivation

In this chapter it is shown that the mean time to failure (MTTF) of oxide-based devices, derived from time-dependent dielectric breakdown (TDDB) measurements, is limited by the surface roughness of the substrate prior to gate thermal growth. dielectric. In the ON state, the saturation current scales with the gate bias, so the oxide field can again limit the efficiency of the device.

Time-Dependent Dielectric Breakdown

In an ideal uncharged oxide, the flat band voltage Vf is equal to the work function difference, so when Vg = Vf b the field in the oxide is zero. In the study of the effect of surface roughness on MTTF presented below, no such extrapolation is necessary because all samples are compared at a given oxide field.

Figure 7.1: (a) Diﬀerent regimes in a current density vs. oxide ﬁeld curve taken at room temperature on a NO-annealed oxide grown on the (0001) Si-face of epitaxial n-type (N doping 5 × 10 15 cm −3 ) 4H-SiC biased in accumulation

Experiments

MTTF can be measured at various oxide fields within the scope of the UN regime. The backside of the samples was etched to expose the SiC surface and allow electrical contact.

Table 7.1: Samples used for roughness and TDDB measurements.

Results and Discussion

The "intrinsic" degradation events for each sample were isolated by assuming a Weibull distribution function for the error probability.12 This gives a line on a probability plot of the cumulative percentage error vs. In particular, theRoughsample yields an MTTF more than one order of magnitude smaller than all the others, consistent with previous studies.3 The polished samples and the C−cap samples show an MTTF of the same order of magnitude as the Epi sample.

Figure 7.4: AFM images of the (0001) SiC surface of implanted samples after activation anneal

Summary

The results associated with this thesis have contributed to the understanding of the SiO2/SiC interface. Another technique that can be used is chemical-mechanical polishing of the semiconductor after activation annealing.