Design and Results

The two LNAs, shown in Fig. 5.2a-b are designed in 65nm CMOS process. The complete circuit of the current-reuse LNA is shown in Fig. 5.3. Unlike in the conventional circuit, the input node in Fig. 5.2b is influenced by the output through an additional path from M₂. Therefore, to reduce the output influence on the input node, a buffer stage consisting of a unity-gain CS (common source) amplifier is added. The buffer stage is realized by the transistorM3shown in Fig. 5.3. A CD (common drain) topology can be used instead of a CS stage as a buffer, however, the former circuit requires more power to reduce the signal loss compared to the latter topology.

5.3 Design and Results

L

_g

C

_ext

V

_DD

L

_s

M

₁

M

₂

LNA2

V

_DD

V

_b1

V

_b2

R

_bias

R

_bias

v

_in

C

_c

C

_c

R

₅₀

R

₅₀

MN M

₃

C

_d

L

_d

Figure 5.3: The complete circuit of the current-reuse LNA. MN is the matching network used to match the output node to 50 Ω load.

Table 5.1: Designed values for transistors and passive components Topology W₁

(µm) W_1c (µm)

W₂ (µm)

W₃ (µm)

L_g (nH)

L_s (nH)

L_d (nH)

C_ext (f F)

C_d (pH)

I_bias (µA)

Power (µW)

LNA-1 44 64 - - 16 2 2 260 2.5 571 514

LNA-2 32 - 16 20 16 2 2 200 2.5 423

+151^* 516

* The First and second stage carries 423 µA and 151 µA respectively and the power is calculated forV_DD=0.9 V.

The designed values of the transistors and the passive elements are given in Table 5.1. The power consumption and the values of the passive elements are maintained same in both the LNA topologies in-order to obtain a fair performance comparison. The LNA-1 carries a current equal to the summation of both the stages in LNA-2. Consequently, LNA-1 and LNA-2 are maintained to operate at same power levels. A tuned tank at the load assumes a bond wire inductor,L_d, along with an on-chip MOM capacitor,C_d. In addition, an external element and a bond wire are assumed for gate (L_g) and source (L_s) inductors respectively both with a Q factor of 50. These are operated with a V_DD of 0.9 V and designed for a center frequency of 2.14 GHz.

High Q inductors are selected that are important factors for gate inductor and tank circuit. As discussed in earlier chapters, low Q on-chip inductors at the gate cannot be used for low power designs as the required large value of inductor may severely degrade the noise figure of the amplifier. Further,

1.5 2 2.5 3 0

10 20 30 40 50 60 70

Frequency (GHz) Effective Transconductance (G meff, mS )

LNA−1 LNA−2

28.8 mS 70 mS

Figure 5.4: Effective transconductances of LNA-1 and LNA-2.

low Q on-chip atL_d would reduce the overall gain and increase the noise figure (NF) particularly in the case of LNA-1. On the other hand, LNA-2 has an advantage compared to LNA-1 that the usage of low Q on-chip for L_d would not affect the overall gain as the total gain is largely decided by the first stage. The required inductor, L_d, can be easily realized by bond-wires as these offers typical inductance per length ratio of 1nH/mm.

The effective transconductance, G_{mef f}, for the two instances are shown in Fig. 5.4. It can be observed that LNA-2 achieves more than two times higher value compared to LNA-1. The LNA-2 has benefitted from the extrag_m of the second transistor,M₂. A schematic simulation depictingS₂₁ and NF of both the LNAs are compared in Fig. 5.5. LNA-2 offers nearly 7 dB higher S₂₁ compared to LNA-1. The gain differences are large because of the differences in their respective transconductances.

However, the noise performance does not show a significant improvement even though LNA-2 exhibits larger gain. It is because there are two transistors that contribute to the noise in LNA-2 compared to LNA-1.

The post-layout simulation for LNA-2 is carried out after RCLK extraction and is given in Fig. 5.6.

TheS21and the obtained NF are 15.8 dB and 1.3 dB respectively. A matching network is used at the output to match a load of 50 Ω for standalone measurement. The obtained S11 and S22 are -15 dB

5.3 Design and Results

1.5 2 2.5 3

−20

−15

−10

−5 0 5 10 15 20

Frequency (GHz) S 21 and NF (dB)

S21 of LNA−1 S21 of LNA−2 NF of LNA−1 NF of LNA−2 S21 = 16.5 dB for LNA−2

S21 = 9.4 dB for LNA−1

NF = 1.1 dB for LNA−2NF = 1.3 dB for LNA−1

Figure 5.5: S21 and NF performance of the LNA-1 and LNA-2

1.5 2 2.5 3

−30

−25

−20

−15

−10

−5 0 5 10 15 20

Frequency (GHz)

S−Parameters and NF (dB)

S21 S11 S22 NF S₂₁=15.8 dB

S11= −15 dB

S21= −27 dB NF=1.3 dB

Figure 5.6: Post-layout simulation after RCLK extraction for LNA-2

and -27 dB respectively. Further, a two-tone test is also carried out with a carrier offset of 10 MHz and it resulted in an IIP3 value of -6 dBm.

The performances of the LNA-2 is compared with the state of art narrow band low-power current- reuse LNAs by using the figure of merit (FOM) which is mentioned in equation (3.23) of chapter 3.

In addition, other low power LNAs which are having a higher FOM from Table 4.5 of chapter 4 are

Table 5.2: Comparison with other current reuse LNAs and other low power LNAs Specification This

work^**

[132] [133] [134] [135] [84] [44]^** [75] [80]

Technology(nm) 65 180 180 180 180 130 130 90 180

Frequency (GHz)

2.14 5 5.4 2 0.4 2.4 2.4 2.4 1

Power (µW) 380 +135^#@

900 2.7

mW

3.8 mW

150 60

µW +1.4 mW^&

240 684 260

P_1dB (dBm) -22.8 -13 -15 -15 -25 N/R -19 -13.5 N/R

Gain or

S₂₁(dB)

15.8 9.2 21⁺ 11 20.2 13.1 18.2 9.7 13.6

NF (dB) 1.3 4.5 2.7^p 1.8 2.8 5.3 4.54 4.36 4.6

IIP3 (dBm) -6 -16 -22^p 0 -8.1 -12.2 -2 -4 +7.2

FOM 39.6 18.9 10.5 24.7 37.8 16^# 44.1 30.6 47.4

Area (µm × µm)

51

×73.6 860

×1100

N/R 175

×50

836

×836

793

×793

N/R 1080

×845

890

×780

**Post-layout simulation results. ^@Core and buffer consume 380 and 135µW respectively. ⁺Higher gain end is selected. ^p Values are not explicitly given rather inferred from the given results.

&Core circuit consumed 60 µW and buffer consumed 1.4 mW. ^#both core and buffer power are considered for FOM calculation. $Buffer power is not included. N/R:Not reported

considered here. The comparison is given in Table 5.2.

The works [84, 132–135] use current-reuse topology while [44, 75, 80] are based on conventional source degenerative CS techniques. It can be observed that the suggested LNA achieves the highest FOM compared to other current-reuse techniques. If core power alone is included then the FOM of the presented technique reaches a value of 42. Further, the presented design offers the lowest noise figure among all the other LNAs considered in Table 5.2. The circuits for [44] and [80] achieve larger FOM mainly because of the improved linearity performances. However, their inferior noise performance is not suitable for applications like LTE standards. The suggested technique in this chapter offers the best noise figure. Its linearity performance, however, has to be improved to make it suitable for LTE applications. In addition, it undergoes PVT variations and hence has to be augmented with compensation techniques that are discussed in chapter 4. Addressing these two issues would make the implementation complete and these will be considered as future work.